tilelink2 Fragmenter: eliminate most of the registers on A
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@ -190,9 +190,10 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// Make the request Irrevocable
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val repeat = Wire(Bool())
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val in_a = Repeater(in.a, repeat)
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// Make the request repeatable
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val repeater = Module(new Repeater(in.a.bits))
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repeater.io.enq <> in.a
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val in_a = repeater.io.deq
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// If this is infront of a single manager, these become constants
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val find = manager.findFast(edgeIn.address(in_a.bits))
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@ -227,12 +228,19 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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when (out.a.fire()) { gennum := new_gennum }
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repeat := !aHasData && aFragnum =/= UInt(0)
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repeater.io.repeat := !aHasData && aFragnum =/= UInt(0)
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out.a <> in_a
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out.a.bits.addr_hi := in_a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes))
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out.a.bits.source := Cat(in_a.bits.source, aFragnum)
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out.a.bits.size := aFrag
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// Optimize away some of the Repeater's registers
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assert (!repeater.io.full || !aHasData)
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out.a.bits.data := in.a.bits.data
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val fullMask = UInt((BigInt(1) << beatBytes) - 1)
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assert (!repeater.io.full || in_a.bits.mask === fullMask)
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out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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@ -10,6 +10,7 @@ class Repeater[T <: Data](gen: T) extends Module
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{
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val io = new Bundle {
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val repeat = Bool(INPUT)
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val full = Bool(OUTPUT)
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val enq = Decoupled(gen).flip
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val deq = Decoupled(gen)
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}
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@ -21,6 +22,7 @@ class Repeater[T <: Data](gen: T) extends Module
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io.deq.valid := io.enq.valid || full
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io.enq.ready := io.deq.ready && !full
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io.deq.bits := Mux(full, saved, io.enq.bits)
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io.full := full
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when (io.enq.fire() && io.repeat) { full := Bool(true); saved := io.enq.bits }
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when (io.deq.fire() && !io.repeat) { full := Bool(false) }
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