rocket: convert scratchpad to TL2
This commit is contained in:
Wesley W. Terpstra
parent
dddb50a942
commit
11121b6f4c
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@ -4,7 +4,9 @@ package rocket
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import Chisel._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.agents._
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import uncore.coherence._
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import uncore.constants._
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@ -495,60 +497,74 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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}
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class ScratchpadSlavePort(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val tl = new ClientUncachedTileLinkIO().flip
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val dmem = new HellaCacheIO
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class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
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val beatBytes = p(XLen)/8
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val node = TLManagerNode(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = List(AddressSet(0x80000000L, p(DataScratchpadSize))),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsPutPartial = TransferSizes(1, beatBytes),
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supportsPutFull = TransferSizes(1, beatBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = beatBytes,
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minLatency = 1))
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lazy val module = new LazyModuleImp(this) with HasCoreParameters {
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val io = new Bundle {
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val tl_in = node.bundleIn
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val dmem = new HellaCacheIO
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}
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val tl_in = io.tl_in(0)
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val edge = node.edgesIn(0)
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val beatBytes = edge.manager.beatBytes
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require(coreDataBits == beatBytes*8)
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require(usingDataScratchpad)
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val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
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val state = Reg(init = s_ready)
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when (io.dmem.resp.valid) { state := s_grant }
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when (tl_in.d.fire()) { state := s_ready }
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when (io.dmem.s2_nack) { state := s_replay }
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when (io.dmem.req.fire()) { state := s_wait }
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val acq = Reg(tl_in.a.bits)
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when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data }
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when (tl_in.a.fire()) { acq := tl_in.a.bits }
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val isWrite = edge.hasData(acq)
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val isRead = !isWrite
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def formCacheReq(acq: TLBundleA) = {
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val req = Wire(new HellaCacheReq)
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// treat all loads as full words, so bytes appear in correct lane
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req.typ := Mux(isRead, log2Ceil(beatBytes), acq.size)
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req.cmd := Mux(isRead, M_XRD, M_XWR)
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req.addr := Mux(isRead, ~(~acq.address | (beatBytes-1)), acq.address)
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req.tag := UInt(0)
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req
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}
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val ready = state === s_ready || tl_in.d.fire()
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io.dmem.req.valid := (tl_in.a.valid && ready) || state === s_replay
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tl_in.a.ready := io.dmem.req.ready && ready
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io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, tl_in.a.bits))
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// this blows. the TL data is already in the correct byte lane, but the D$
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// expects right-justified store data, so that it can steer the bytes.
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io.dmem.s1_data := new LoadGen(acq.size, Bool(false), acq.address(log2Ceil(beatBytes)-1,0), acq.data, Bool(false), beatBytes).data
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io.dmem.s1_kill := false
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io.dmem.invalidate_lr := false
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// place AMO data in correct word lane
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val minAMOBytes = 4
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val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
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val alignedGrantData = Mux(acq.size <= log2Ceil(minAMOBytes), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
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tl_in.d.valid := io.dmem.resp.valid || state === s_grant
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tl_in.d.bits := Mux(isRead,
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edge.AccessAck(acq, UInt(0), alignedGrantData),
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edge.AccessAck(acq, UInt(0)))
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}
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val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
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val state = Reg(init = s_ready)
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when (io.dmem.resp.valid) { state := s_grant }
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when (io.tl.grant.fire()) { state := s_ready }
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when (io.dmem.s2_nack) { state := s_replay }
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when (io.dmem.req.fire()) { state := s_wait }
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val acq = Reg(io.tl.acquire.bits)
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when (io.dmem.resp.valid) { acq.data := io.dmem.resp.bits.data }
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when (io.tl.acquire.fire()) { acq := io.tl.acquire.bits }
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val isRead = acq.isBuiltInType(Acquire.getType)
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val isWrite = acq.isBuiltInType(Acquire.putType)
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assert(state === s_ready || isRead || isWrite)
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require(coreDataBits == acq.tlDataBits)
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require(usingDataScratchpad)
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def formCacheReq(acq: Acquire) = {
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val req = Wire(new HellaCacheReq)
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// treat all loads as full words, so bytes appear in correct lane
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req.typ := Mux(isRead, log2Ceil(acq.tlDataBytes), acq.op_size())
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req.cmd := acq.op_code()
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req.addr := Mux(isRead, ~(~acq.full_addr() | (acq.tlDataBytes-1)), acq.full_addr())
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req.tag := UInt(0)
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req
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}
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val ready = state === s_ready || io.tl.grant.fire()
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io.dmem.req.valid := (io.tl.acquire.valid && ready) || state === s_replay
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io.tl.acquire.ready := io.dmem.req.ready && ready
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io.dmem.req.bits := formCacheReq(Mux(state === s_replay, acq, io.tl.acquire.bits))
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// this blows. the TL data is already in the correct byte lane, but the D$
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// expects right-justified store data, so that it can steer the bytes.
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io.dmem.s1_data := new LoadGen(acq.op_size(), Bool(false), acq.addr_byte(), acq.data, Bool(false), acq.tlDataBytes).data
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io.dmem.s1_kill := false
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io.dmem.invalidate_lr := false
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// place AMO data in correct word lane
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val minAMOBytes = 4
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val grantData = Mux(io.dmem.resp.valid, io.dmem.resp.bits.data, acq.data)
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val alignedGrantData = Mux(acq.op_size() <= log2Ceil(minAMOBytes), Fill(coreDataBytes/minAMOBytes, grantData(8*minAMOBytes-1, 0)), grantData)
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io.tl.grant.valid := io.dmem.resp.valid || state === s_grant
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io.tl.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = acq.getBuiltInGrantType(),
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client_xact_id = acq.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = acq.addr_beat,
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data = alignedGrantData)
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}
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@ -27,40 +27,43 @@ case class RoccParameters(
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case class TileBundleConfig(
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nCachedTileLinkPorts: Int,
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nUncachedTileLinkPorts: Int,
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xLen: Int,
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hasSlavePort: Boolean)
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xLen: Int)
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class TileIO(c: TileBundleConfig)(implicit p: Parameters) extends Bundle {
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class TileIO(c: TileBundleConfig, node: Option[TLInwardNode] = None)(implicit p: Parameters) extends Bundle {
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val cached = Vec(c.nCachedTileLinkPorts, new ClientTileLinkIO)
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val uncached = Vec(c.nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
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val hartid = UInt(INPUT, c.xLen)
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val interrupts = new TileInterrupts().asInput
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val slave = c.hasSlavePort.option(new ClientUncachedTileLinkIO().flip)
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val slave = node.map(_.inward.bundleIn)
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val resetVector = UInt(INPUT, c.xLen)
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override def cloneType = new TileIO(c).asInstanceOf[this.type]
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}
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abstract class TileImp(l: LazyTile)(implicit p: Parameters) extends LazyModuleImp(l) {
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val io: TileIO
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}
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abstract class LazyTile(implicit p: Parameters) extends LazyModule {
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val nCachedTileLinkPorts = p(NCachedTileLinkPorts)
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val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts)
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val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
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val bc = TileBundleConfig(
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nCachedTileLinkPorts = nCachedTileLinkPorts,
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nUncachedTileLinkPorts = nUncachedTileLinkPorts,
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xLen = p(XLen),
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hasSlavePort = p(DataScratchpadSize) > 0)
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xLen = p(XLen))
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val io: TileIO
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}
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abstract class LazyTile(implicit p: Parameters) extends LazyModule {
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val module: TileImp
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}
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class RocketTile(implicit p: Parameters) extends LazyTile {
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val slave = if (p(DataScratchpadSize) == 0) None else Some(TLOutputNode())
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val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
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(slave zip scratch) foreach { case (node, lm) => node := lm.node }
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lazy val module = new TileImp(this) {
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val io = new TileIO(bc)
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val io = new TileIO(bc, slave)
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val buildRocc = p(BuildRoCC)
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val usingRocc = !buildRocc.isEmpty
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val nRocc = buildRocc.size
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@ -146,11 +149,7 @@ class RocketTile(implicit p: Parameters) extends LazyTile {
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core.io.ptw <> ptw.io.dpath
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}
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io.slave foreach { case slavePort =>
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val adapter = Module(new ScratchpadSlavePort()(dcacheParams))
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adapter.io.tl <> TileLinkFragmenter(slavePort)
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adapter.io.dmem +=: dcPorts
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}
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scratch.foreach { lm => lm.module.io.dmem +=: dcPorts }
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require(dcPorts.size == core.dcacheArbPorts)
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val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
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@ -5,9 +5,11 @@ import diplomacy._
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package object tilelink2
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{
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type TLInwardNode = InwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
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type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
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type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
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def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
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def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
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def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
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