riscv/rocket-chip
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rocketchip: bundle (=> B) need not be delayed; Module is constructed later

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This commit is contained in:
Wesley W. Terpstra 2016-10-25 14:28:52 -07:00
parent 0dbda2f07d
commit 0ae45d0f24
5 changed files with 9 additions and 10 deletions
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2
src/main/scala/coreplex/BaseCoreplex.scala
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@ -76,7 +76,7 @@ abstract class BaseCoreplexBundle(val c: CoreplexConfig)(implicit val p: Paramet
}
abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
c: CoreplexConfig, l: L, b: => B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
c: CoreplexConfig, l: L, b: B)(implicit val p: Parameters) extends LazyModuleImp(l) with HasCoreplexParameters {
val outer: L = l
val io: B = b

4
src/main/scala/coreplex/Coreplex.scala
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@ -34,7 +34,7 @@ class DefaultCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends BaseCor
class DefaultCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle](
c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
with DirectConnection
/////
@ -81,5 +81,5 @@ class MultiClockCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extend
with TileClockResetBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle](
c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p)
with AsyncConnection

2
src/main/scala/groundtest/Coreplex.scala
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@ -11,6 +11,6 @@ class GroundTestCoreplex(c: CoreplexConfig)(implicit p: Parameters) extends Base
class GroundTestCoreplexBundle(c: CoreplexConfig)(implicit p: Parameters) extends BaseCoreplexBundle(c)(p)
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle](
c: CoreplexConfig, l: L, b: => B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
c: CoreplexConfig, l: L, b: B)(implicit p: Parameters) extends BaseCoreplexModule(c, l, b)(p) with DirectConnection {
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}

7
src/main/scala/rocketchip/BaseTop.scala
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@ -72,10 +72,9 @@ abstract class BaseTopBundle(val p: Parameters) extends Bundle {
}
abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val p: Parameters, l: L, b: => B) extends LazyModuleImp(l) {
val outer: L = l
val io: B = b
val p: Parameters,
val outer: L,
val io: B) extends LazyModuleImp(outer) {
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = Wire(coreplex.io)

4
src/main/scala/rocketchip/ExampleTop.scala
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@ -29,7 +29,7 @@ class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
with PeripheryMasterMMIOBundle
with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B) extends BaseTopModule(p, l, b)
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: B) extends BaseTopModule(p, l, b)
with PeripheryBootROMModule
with PeripheryDebugModule
with PeripheryExtInterruptsModule
@ -49,5 +49,5 @@ class ExampleTopWithTestRAM(q: Parameters) extends ExampleTop(q)
class ExampleTopWithTestRAMBundle(p: Parameters) extends ExampleTopBundle(p)
with PeripheryTestRAMBundle
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: => B) extends ExampleTopModule(p, l, b)
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: B) extends ExampleTopModule(p, l, b)
with PeripheryTestRAMModule