diplomacy: add BlindNodes for use as external ports
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@ -208,12 +208,28 @@ class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po:
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
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{
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require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
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override lazy val bundleIn = { require(false, s"${name} has no bundleIn; try bundleOut?"); bundleOut }
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}
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class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
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{
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require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
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override lazy val bundleOut = { require(false, s"${name} has no bundleOut; try bundleIn?"); bundleIn }
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}
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class BlindOutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI)
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extends SimpleNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, 1 to 1)
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{
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override val flip = true
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override lazy val bundleOut = bundleIn
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}
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class BlindInputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO)
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extends SimpleNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, 1 to 1, 0 to 0)
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{
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override val flip = true
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override lazy val bundleIn = bundleOut
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}
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class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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@ -30,18 +30,23 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
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pu.copy(slaves = pu.slaves.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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// Nodes implemented inside modules
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case class AXI4IdentityNode() extends IdentityNode(AXI4Imp)
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case class AXI4OutputNode() extends OutputNode(AXI4Imp)
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case class AXI4InputNode() extends InputNode(AXI4Imp)
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case class AXI4MasterNode(portParams: AXI4MasterPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(AXI4Imp)(portParams, numPorts)
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case class AXI4SlaveNode(portParams: AXI4SlavePortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SinkNode(AXI4Imp)(portParams, numPorts)
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case class AXI4AdapterNode(
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masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters,
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slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters,
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numMasterPorts: Range.Inclusive = 1 to 1,
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numSlavePorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(AXI4Imp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
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// Nodes passed from an inner module
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case class AXI4OutputNode() extends OutputNode(AXI4Imp)
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case class AXI4InputNode() extends InputNode(AXI4Imp)
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// Nodes used for external ports
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case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
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case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
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@ -89,10 +89,8 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
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}
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}
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// Nodes implemented inside modules
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case class TLIdentityNode() extends IdentityNode(TLImp)
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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case class TLClientNode(portParams: TLClientPortParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(portParams, numPorts)
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case class TLManagerNode(portParams: TLManagerPortParameters, numPorts: Range.Inclusive = 1 to 1)
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@ -117,6 +115,14 @@ case class TLAdapterNode(
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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// Nodes passed from an inner module
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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// Nodes used for external ports
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case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
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case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
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/** Synthesizeable unit tests */
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import unittest._
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