tilelink2 ToAXI4: must create irrevocable D for now
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@ -217,9 +217,12 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
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// Give R higher priority than B
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val r_wins = out.r.valid || r_holds_d
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out.r.ready := in.d.ready
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out_b.ready := in.d.ready && !r_wins
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in.d.valid := Mux(r_wins, out.r.valid, out_b.valid)
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val in_d = Wire(in.d)
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in.d <> Queue.irrevocable(in_d, entries=1, flow=combinational)
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out.r.ready := in_d.ready
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out_b.ready := in_d.ready && !r_wins
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in_d.valid := Mux(r_wins, out.r.valid, out_b.valid)
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val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
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val b_error = out_b.bits.resp =/= AXI4Parameters.RESP_OKAY
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@ -227,8 +230,8 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
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val r_d = edgeIn.AccessAck(r_addr_lo, r_sink, r_source, r_size, UInt(0), r_error)
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val b_d = edgeIn.AccessAck(b_addr_lo, b_sink, b_source, b_size, b_error)
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in.d.bits := Mux(r_wins, r_d, b_d)
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in.d.bits.data := out.r.bits.data // avoid a costly Mux
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in_d.bits := Mux(r_wins, r_d, b_d)
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in_d.bits.data := out.r.bits.data // avoid a costly Mux
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// Tie off unused channels
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in.b.valid := Bool(false)
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