riscv/rocket-chip
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Debug: make address configurable

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This commit is contained in:
Wesley W. Terpstra 2016-10-26 13:27:35 -07:00
parent c3dacca39a
commit bddfa4d69b
2 changed files with 4 additions and 4 deletions
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4
src/main/scala/coreplex/BaseCoreplex.scala
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@ -51,7 +51,7 @@ case class CoreplexConfig(
abstract class BaseCoreplex(c: CoreplexConfig)(implicit val p: Parameters) extends LazyModule with HasCoreplexParameters {
val debugLegacy = LazyModule(new TLLegacy()(outerMMIOParams))
val debugModule = LazyModule(new TLDebugModule(p(XLen)/8))
val debugModule = LazyModule(new TLDebugModule())
debugModule.node :=
TLHintHandler()(
TLBuffer()(
@ -121,7 +121,7 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle](
// and coherence manager(s) to the other side
l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner // legacy goes here (not mmioManager)
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, c.nMemChannels)(outerMemParams))

4
src/main/scala/uncore/devices/Debug.scala
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@ -823,8 +823,8 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
*
*/
class TLDebugModule(beatBytes: Int) (implicit p: Parameters)
extends TLRegisterRouter(0x0, beatBytes=beatBytes)(
class TLDebugModule(address: BigInt = 0)(implicit p: Parameters)
extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8)(
new TLRegBundle(p, _ ) with DebugModuleBundle)(
new TLRegModule(p, _, _) with DebugModule)