riscv/rocket-chip
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  • 1b158d2caf
         Merge pull request #1244 from freechipsproject/dtim-priority Andrew Waterman 2018-02-20 14:19:21 -0800
  • 1bac2cbdf8 Give Rocket priority over DTIM TL port Andrew Waterman 2018-02-20 11:23:10 -0800
  • db35f45bf7
         Merge pull request #1242 from freechipsproject/unnamed_reg_fix Megan Wachs 2018-02-16 14:27:53 -0800
  • 135f06cefc Clarify errors, init jtag error code to zero (#1241) Schuyler Eldridge 2018-02-16 16:03:51 -0500
  • 5affd3bec2 RegFieldDesc: fix the output produced for undescribed registers Megan Wachs 2018-02-16 10:24:12 -0800
  • cf7cd03d64
         Merge pull request #1239 from freechipsproject/reduce_debug_flags Megan Wachs 2018-02-16 08:53:41 -0800
  • bb1976552f
         Merge pull request #1238 from freechipsproject/error-bifurcate Wesley W. Terpstra 2018-02-15 22:19:27 -0800
  • d72abb7a12
         Debug: revert change to how flags are named Megan Wachs 2018-02-15 21:49:32 -0800
  • dcfbdabe60 CacheCork: better document edge conditions Wesley W. Terpstra 2018-02-15 19:14:30 -0800
  • ecd069dca4 tilelink: allow FIFO caches Wesley W. Terpstra 2018-02-15 19:09:37 -0800
  • acecc407a5 HellaCache: we do NOT really support probe below the block size! Wesley W. Terpstra 2018-02-15 19:08:43 -0800
  • c34b940d9a
         ElaborationArtefacts: revert unintentional change Megan Wachs 2018-02-15 14:23:54 -0800
  • e0c3b22d61
         RegFieldDesc: same string used to insert/compare Megan Wachs 2018-02-15 14:23:27 -0800
  • b95f68447f RegFieldDesc: Prevent different RegField JSONS from overwriting eachother. Megan Wachs 2018-02-15 14:01:47 -0800
  • 64d3731e45 RegFieldDesc: don't put characters into names that need to be sanitized Megan Wachs 2018-02-15 13:25:06 -0800
  • 197699b93a Debug: don't need to fully populate flags array Megan Wachs 2018-02-15 13:23:51 -0800
  • fa412246b3 Error: don't be an exception wrt. caching Wesley W. Terpstra 2018-02-14 22:51:37 -0800
  • e2e678d53d
         Merge pull request #1183 from freechipsproject/regfield_descriptions Megan Wachs 2018-02-12 14:25:06 -0800
  • 6f70d25ef9
         Merge pull request #1184 from freechipsproject/regfield_json Megan Wachs 2018-02-12 12:00:01 -0800
  • de91672e9a RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields Megan Wachs 2018-02-12 08:32:52 -0800
  • 7bf0121f07 PLIC: correct some descriptions Megan Wachs 2018-02-12 08:31:29 -0800
  • 08acbe1a29 RegFieldDesc: Clean up both descriptions and JSON presentations Megan Wachs 2018-02-11 23:57:57 -0800
  • 5ab4204e8a RegField: the JSON will just leave things out of type None Megan Wachs 2018-01-10 15:53:13 -0800
  • 3b44f380d8 TLRegMapper: emit a JSON file describing the register fields Megan Wachs 2018-01-08 18:13:00 -0800
  • 256f8ffc6b Clint: Annotate regmap with RegFieldDesc Megan Wachs 2018-02-11 21:33:09 -0800
  • 718c88a8f9 PLIC: Annotate regmap with RegFieldDescs Megan Wachs 2018-02-11 21:05:17 -0800
  • 13b120fb01 Debug: Annotate regmaps with RegFieldDescs Megan Wachs 2018-02-10 20:11:24 -0800
  • 7abf6e1c8a RegMapper: Update cover props to use new RegFieldDesc objects Megan Wachs 2018-02-10 13:17:38 -0800
  • 4ab1585a78 Register Field: Add a more verbose description object Megan Wachs 2018-01-08 11:20:37 -0800
  • 1bfdfacda0
         Merge pull request #1234 from grebe/bindFixup Henry Cook 2018-02-09 15:59:51 -0800
  • ac62bf7f22 Use bind from global namespace Paul Rigge 2018-02-09 14:16:20 -0800
  • 9a56221566
         Merge pull request #1192 from seldridge/auto-plusargs Henry Cook 2018-02-08 18:29:31 -0800
  • fe277cf6f0
         Merge branch 'master' into auto-plusargs Henry Cook 2018-02-06 18:38:44 -0800
  • 9f6d586e8c
         Add PLIC covers (#1229) Andrew Waterman 2018-02-06 17:33:33 -0800
  • 36cba65e60
         Merge pull request #1228 from freechipsproject/no-mul Andrew Waterman 2018-02-06 15:38:20 -0800
  • efc6c9cbd3 Let user of CSRFile decide when to set tval Andrew Waterman 2018-02-06 14:05:03 -0800
  • a59fc3bdaa Teach MulDiv to do either mul-only or div-only by setting unroll=0 Andrew Waterman 2018-02-05 17:49:33 -0800
  • 69441930b5 Rationalize ALU function encoding Andrew Waterman 2018-02-05 17:50:01 -0800
  • c1eb795aba move sbt-launch to match project/build.properties (#1222) Colin Schmidt 2018-02-02 17:13:05 -0800
  • e26363a176
         Don't pass deprecated -ffaaf option to firrtl (#1221) Andrew Waterman 2018-02-01 14:46:38 -0800
  • 18e3bf3701 Bump Firrtl (#1219) Jack Koenig 2018-01-31 14:31:54 -0800
  • 5294523551
         Keep io.cpu.s1_data for visibility (#1218) solomatnikov 2018-01-31 14:31:42 -0800
  • ad58b37437
         Merge pull request #1215 from freechipsproject/config-altermap Henry Cook 2018-01-31 14:22:17 -0800
  • b1fa19e801 bump hardfloat for scala 2.11.12 (#1216) Henry Cook 2018-01-30 20:42:36 -0800
  • 7dad486707 util: updates to internal Generator API Henry Cook 2018-01-30 15:19:37 -0800
  • bd50a1a4bc config: remove deprecated Parameters.root Henry Cook 2017-10-25 11:54:47 -0700
  • 46751bedeb config: MapParameters are back in style Henry Cook 2017-10-25 11:17:32 -0700
  • f4853c4f63
         Add cover properties to Core CSRs (#1212) Jacob Chang 2018-01-30 00:01:19 -0800
  • b5ff853e86
         Sign-extend the depc CSR (#1209) Andrew Waterman 2018-01-26 12:07:33 -0800
  • 8d8e4e1399
         Merge pull request #1196 from freechipsproject/interrupt-cover Andrew Waterman 2018-01-25 18:06:13 -0800
  • d2399b6d0e Cover all exceptions and interrupts Andrew Waterman 2018-01-16 00:45:50 -0800
  • a749326deb
         Add cover points to registers (#1208) Jacob Chang 2018-01-24 21:37:24 -0800
  • 94d2edceb9
         Merge pull request #1205 from freechipsproject/fpu-cover Andrew Waterman 2018-01-23 18:49:45 -0800
  • 7a0252fdfc Add some covers for FPU structural hazards Andrew Waterman 2018-01-23 16:27:46 -0800
  • a2ca82f92c Add VM covers Andrew Waterman 2018-01-23 16:13:35 -0800
  • dcda98dcaf
         Disable coverage collection for testbench related verilog files (#1204) Jacob Chang 2018-01-22 16:40:38 -0800
  • c32150b994
         ResetCatchAndSync: work also in the context of a RawModule (#1202) Wesley W. Terpstra 2018-01-19 19:45:52 -0800
  • f6f5606f8e
         diplomacy: run user instantiate() method after nodes are initialized (#1198) Wesley W. Terpstra 2018-01-18 14:57:47 -0800
  • 5cc1411e14
         Merge pull request #1199 from freechipsproject/require-messages Henry Cook 2018-01-18 14:53:25 -0800
  • bf5dd6dac3
         Replace Parameters in cover with globally setable implementation (#1200) Jack Koenig 2018-01-18 14:45:36 -0800
  • 24c1235500 rocket: add address to tlb permissions require msgs Henry Cook 2018-01-18 10:31:51 -0800
  • 5854fb5f7c
         SourceShrinker improvements (#1197) Wesley W. Terpstra 2018-01-17 18:02:19 -0800
  • 338e453a91
         JTAG: Use new withClock way of overriding clocks (#1072) Megan Wachs 2018-01-17 13:59:05 -0800
  • 355d3b15e8 Merge 'origin/master' into auto-plusargs Schuyler Eldridge 2018-01-16 15:45:53 -0500
  • 80ca018e3a
         Add cover points for BusErrorUnit (#1193) Jacob Chang 2018-01-15 18:00:29 -0800
  • 04af785a5f Emit plusArgs for unit tests Schuyler Eldridge 2018-01-15 17:54:40 -0500
  • 09c1d034fa Explicitly name PlusArg serializers as *_cHeader Schuyler Eldridge 2018-01-15 17:00:12 -0500
  • cfd49f87c1 Use longname for ElaborationArtefact emission Schuyler Eldridge 2018-01-15 16:53:36 -0500
  • 6c6afc5bc9
         Merge pull request #1191 from edcote/patch-2 Megan Wachs 2018-01-15 13:33:27 -0800
  • e52d52ae99 Link PlusArg to emulator command line options Schuyler Eldridge 2018-01-15 14:21:09 -0500
  • 904f0f3d93
         enhance error message when debug enabled Edmond Cote 2018-01-13 13:35:52 -0800
  • ff11673a9c
         remove string type ambiguity in header Edmond Cote 2018-01-13 13:29:22 -0800
  • 8799508b1f
         Merge pull request #1179 from freechipsproject/refactored_rbb Megan Wachs 2018-01-12 10:34:48 -0800
  • b8219425d8 Fix spelling and capitalization in README.md (#1182) Jordan Danford 2018-01-10 16:52:07 -0700
  • 5fe0bb0d6a Merge remote-tracking branch 'origin/master' into refactored_rbb Megan Wachs 2018-01-09 21:34:14 -0800
  • f5211765e9
         Merge pull request #1177 from freechipsproject/dont-touch-2 Henry Cook 2018-01-09 15:13:55 -0800
  • c152962642 Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) pentin-as 2018-01-09 16:06:43 -0500
  • 42e5e92d43
         Update TestDriver module to support FSDB Edmond Cote 2018-01-09 09:54:34 -0800
  • 15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts Henry Cook 2018-01-08 19:38:10 -0800
  • 11e5b620f8 tile: disable more monitors on slave port Henry Cook 2018-01-08 18:41:55 -0800
  • 5075a93e6c util: dontTouch work-around for zero width aggregates Henry Cook 2018-01-08 15:58:28 -0800
  • 7fc8337cdb
         Merge pull request #1180 from freechipsproject/addrwregdesc Albert Huntington 2018-01-08 09:44:44 -0800
  • a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb Megan Wachs 2018-01-08 09:11:27 -0800
  • 4fd4ae38e3
         Merge pull request #1176 from freechipsproject/fix-tl-port Henry Cook 2018-01-05 20:37:44 -0800
  • 3525489fff
         Merge pull request #1174 from freechipsproject/error-device-tracked Henry Cook 2018-01-05 17:17:22 -0800
  • 427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs Megan Wachs 2018-01-03 16:55:48 -0800
  • 76c5fd0c0c travis: Use newer infrastructure, but require sudo for additional disk space. Megan Wachs 2017-12-22 16:20:12 -0800
  • e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. Megan Wachs 2017-12-19 17:13:08 -0800
  • b643f3dca6 debug regressions: some whitespace and null ptr cleanup Megan Wachs 2017-12-19 14:57:31 -0800
  • 96dd5d8c38 Emulator example clarifications Schuyler Eldridge 2017-11-30 12:41:23 -0500
  • 7ae6bf7611 Arguments clarification, add examples Schuyler Eldridge 2017-11-18 19:20:44 -0500
  • 1aa87f6578 Make emulator.cc understand HTIF arguments Schuyler Eldridge 2017-03-20 00:16:18 -0400
  • 3ead9a5d2d Move check on VCS inside riscv-fesvr Schuyler Eldridge 2017-03-20 00:13:10 -0400
  • a97add954a Async Reg: Doesn't properly reset for Verilator. Megan Wachs 2017-12-01 17:43:01 -0800
  • 9df3604007 emulator: No reason not to emit waveforms during reset Megan Wachs 2017-12-01 17:07:28 -0800
  • 024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved Megan Wachs 2017-11-21 15:46:44 -0800
  • 1d3fa07c44 debug: print failures when debug tests fail, so we can see why it is failing on Travis Megan Wachs 2017-11-17 16:03:16 -0800
  • 8425086f98 Allow rwReg to pass name and description to RegField for documentation. Albert Huntington 2018-01-05 16:59:58 -0800
  • 9b234216f0 debug: Install pexpect package for travis regressions Megan Wachs 2017-11-17 08:05:44 -0800
  • 1549ecfb3f debug: explicitly clone riscv-tests to get to gdbserver.py Megan Wachs 2017-11-16 15:25:41 -0800