Merge pull request #1238 from freechipsproject/error-bifurcate
Error: don't be an exception wrt. caching
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commit
bb1976552f
@ -10,7 +10,7 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int)
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case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int, acquire: Boolean = false)
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{
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require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
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}
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@ -26,10 +26,10 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
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Seq(TLManagerParameters(
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address = params.address,
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resources = device.reg("mem"),
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regionType = RegionType.UNCACHEABLE,
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regionType = if (params.acquire) RegionType.TRACKED else RegionType.UNCACHEABLE,
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executable = true,
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supportsAcquireT = xfer,
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supportsAcquireB = xfer,
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supportsAcquireT = if (params.acquire) xfer else TransferSizes.none,
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supportsAcquireB = if (params.acquire) xfer else TransferSizes.none,
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supportsGet = xfer,
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supportsPutPartial = xfer,
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supportsPutFull = xfer,
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@ -52,19 +52,15 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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val (in, edge) = node.in(0)
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val a = Queue(in.a, 1)
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val c = Queue(in.c, 1)
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val da = Wire(in.d)
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val dc = Wire(in.d)
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val a_last = edge.last(a)
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val c_last = edge.last(c)
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val da_last = edge.last(da)
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val dc_last = edge.last(dc)
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a.ready := (da.ready && da_last) || !a_last
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da.valid := a.valid && a_last
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val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant)
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val a_opcodes = Vec(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
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da.bits.opcode := a_opcodes(a.bits.opcode)
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da.bits.param := UInt(0) // toT, but error grants must be handled transiently (ie: you don't keep permissions)
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da.bits.size := a.bits.size
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@ -73,21 +69,31 @@ class TLError(params: ErrorParams, beatBytes: Int = 4)(implicit p: Parameters)
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da.bits.data := UInt(0)
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da.bits.error := Bool(true)
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c.ready := (dc.ready && dc_last) || !c_last
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dc.valid := c.valid && c_last
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if (params.acquire) {
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val c = Queue(in.c, 1)
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val dc = Wire(in.d)
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dc.bits.opcode := ReleaseAck
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dc.bits.param := Vec(toB, toN, toN)(c.bits.param)
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dc.bits.size := c.bits.size
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dc.bits.source := c.bits.source
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dc.bits.sink := UInt(0)
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dc.bits.data := UInt(0)
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dc.bits.error := Bool(true)
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val c_last = edge.last(c)
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val dc_last = edge.last(dc)
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// Combine response channels
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TLArbiter.lowest(edge, in.d, dc, da)
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c.ready := (dc.ready && dc_last) || !c_last
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dc.valid := c.valid && c_last
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// We never probe or issue B requests; we are UNCACHED
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dc.bits.opcode := ReleaseAck
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dc.bits.param := Vec(toB, toN, toN)(c.bits.param)
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dc.bits.size := c.bits.size
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dc.bits.source := c.bits.source
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dc.bits.sink := UInt(0)
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dc.bits.data := UInt(0)
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dc.bits.error := Bool(true)
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// Combine response channels
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TLArbiter.lowest(edge, in.d, dc, da)
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} else {
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in.d <> da
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}
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// We never probe or issue B requests
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in.b.valid := Bool(false)
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// Sink GrantAcks
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@ -163,7 +163,7 @@ abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModul
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TLClientParameters(
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name = s"Core ${hartid} DCache",
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sourceId = IdRange(0, firstMMIO),
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supportsProbe = TransferSizes(1, cfg.blockBytes)),
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supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)),
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TLClientParameters(
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name = s"Core ${hartid} DCache MMIO",
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sourceId = IdRange(firstMMIO, firstMMIO+cfg.nMMIOs),
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@ -26,10 +26,10 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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val clients = edgeIn.client.clients
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val caches = clients.filter(_.supportsProbe)
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require (clients.size == 1 || caches.size == 0 || unsafe, "Only one client can safely use a TLCacheCork")
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require (caches.size <= 1 || unsafe, "Only one caching client allowed")
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require (clients.size == 1 || caches.size == 0 || unsafe, s"Only one client can safely use a TLCacheCork; ${clients.map(_.name)}")
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require (caches.size <= 1 || unsafe, s"Only one caching client allowed; ${clients.map(_.name)}")
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edgeOut.manager.managers.foreach { case m =>
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require (!m.supportsAcquireB || unsafe, "Cannot support caches beyond the Cork")
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require (!m.supportsAcquireB || unsafe, s"Cannot support caches beyond the Cork; ${m.name}")
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require (m.regionType <= RegionType.UNCACHED)
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}
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@ -39,8 +39,15 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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// A caveat is that we get Acquire+Release with the same source and must keep the
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// source unique after transformation onto the A channel.
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// The coding scheme is:
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// Put: 1, Release: 0 => AccessAck
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// *: 0, Acquire: 1 => AccessAckData
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// Release, AcquireBlock.BtoT, AcquirePerm => instant response
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// Put{Full,Partial}Data: 1, ReleaseData: 0 => AccessAck
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// {Arithmetic,Logical}Data,Get: 0, Acquire: 1 => AccessAckData
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// Hint:0 => HintAck
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// The CacheCork can potentially send the same source twice if a client sends
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// simultaneous Release and AMO/Get with the same source. It will still correctly
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// decode the messages based on the D.opcode, but the double use violates the spec.
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// Fortunately, no masters we know of behave this way!
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// Take requests from A to A or D (if BtoT Acquire)
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val a_a = Wire(out.a)
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@ -40,7 +40,7 @@ case class TLManagerParameters(
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require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
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// Make sure that the regionType agrees with the capabilities
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require (!supportsAcquireB || regionType >= RegionType.UNCACHEABLE) // acquire -> uncached, tracked, cached
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require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
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require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
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require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
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@ -186,7 +186,7 @@ case class TLClientParameters(
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name: String,
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[BaseNode] = Seq(),
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requestFifo: Boolean = false, // only a request, not a requirement
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requestFifo: Boolean = false, // only a request, not a requirement. applies to A, not C.
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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@ -204,8 +204,6 @@ case class TLClientParameters(
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require (supportsProbe.contains(supportsPutFull))
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require (supportsProbe.contains(supportsPutPartial))
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require (supportsProbe.contains(supportsHint))
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// If you need FIFO, you better not be TL-C (due to independent A vs. C order)
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require (!requestFifo || !supportsProbe)
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val maxTransfer = List(
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supportsProbe.max,
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