riscv/rocket-chip
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Add cover points for BusErrorUnit (#1193)

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Jacob Chang 2018-01-15 18:00:29 -08:00 committed by GitHub
parent 6c6afc5bc9
commit 80ca018e3a
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1 changed files with 2 additions and 0 deletions
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src/main/scala/rocket/BusErrorUnit.scala
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@ -12,6 +12,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.property._
trait BusErrors extends Bundle {
def toErrorList: List[Option[Valid[UInt]]]
@ -59,6 +60,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
cause := i
value := s.get.bits
}
cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered")
}
}