riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Add cover points for BusErrorUnit (#1193)

This commit is contained in:
Jacob Chang 2018-01-15 18:00:29 -08:00 committed by GitHub
parent 6c6afc5bc9
commit 80ca018e3a
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/rocket/BusErrorUnit.scala
View File

@ -12,6 +12,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.property._
trait BusErrors extends Bundle {
def toErrorList: List[Option[Valid[UInt]]]
@ -59,6 +60,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
cause := i
value := s.get.bits
}
cover(en, s"BusErrorCause_$i", s"Core;;BusErrorCause $i covered")
}
}