Merge pull request #1177 from freechipsproject/dont-touch-2
Make more use of chisel3.experimental.DontTouch
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commit
f5211765e9
@ -3,6 +3,7 @@
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package freechips.rocketchip.coreplex
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import Chisel._
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import chisel3.experimental.dontTouch
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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@ -37,9 +38,9 @@ trait HasTilesModuleImp extends LazyModuleImp
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vectors.head.getWidth
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}
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val tile_inputs = Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
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val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
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case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
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})))
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})))) // dontTouch keeps constant prop from sucking these signals into the tile
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// Unconditionally wire up the non-diplomatic tile inputs
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outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>
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@ -118,18 +118,14 @@ trait HasRocketTiles extends HasTiles
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def tileSlaveBuffering: TLInwardNode = rocket {
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val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
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crossing.crossingType match {
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case _: SynchronousCrossing => rocket.slaveNode // requirement already checked
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case _: AsynchronousCrossing => rocket.slaveNode
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case _: RationalCrossing =>
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if (tp.boundaryBuffers) {
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DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node }
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} else {
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rocket.slaveNode
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}
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case RationalCrossing(_) if (tp.boundaryBuffers) => rocket.slaveNode :*= slaveBuffer.node
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case _ => rocket.slaveNode
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}
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}
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pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(tileSlaveBuffering :*= rocket.crossTLIn) }
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pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)( DisableMonitors { implicit p =>
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tileSlaveBuffering :*= rocket.crossTLIn
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})}
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// Handle all the different types of interrupts crossing to or from the tile:
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// 1. Debug interrupt is definitely asynchronous in all cases.
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@ -151,7 +147,7 @@ trait HasRocketTiles extends HasTiles
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if (tp.core.useVM) periphIntNode := plic.intnode // seip
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// 3. local interrupts never cross
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// this.intInwardNode is wired up externally // lip
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// rocket.intInwardNode is wired up externally // lip
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// 4. conditional crossing from core to PLIC
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FlipRendering { implicit p =>
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@ -4,6 +4,7 @@
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package freechips.rocketchip.rocket
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import Chisel._
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import chisel3.experimental.dontTouch
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.coreplex._
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import freechips.rocketchip.diplomacy._
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@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
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implicit val edge = outer.node.edges.out(0)
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val (tl_out, _) = outer.node.out(0)
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val io = IO(new HellaCacheBundle(outer))
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dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
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private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
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fifoManagers.foreach { m =>
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@ -135,7 +135,6 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
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protected val tlMasterXbar = LazyModule(new TLXbar)
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protected val tlSlaveXbar = LazyModule(new TLXbar)
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protected val intXbar = LazyModule(new IntXbar)
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protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
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def connectTLSlave(node: TLNode, bytes: Int) {
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DisableMonitors { implicit p =>
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@ -22,6 +22,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
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trait HasExternalInterrupts { this: BaseTile =>
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val intInwardNode = intXbar.intnode
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protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
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intSinkNode := intXbar.intnode
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val intcDevice = new Device {
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@ -66,7 +66,7 @@ class RocketTile(
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// TODO: this doesn't block other masters, e.g. RoCCs
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tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
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masterNode :=* tlOtherMastersNode
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tlSlaveXbar.node :*= slaveNode
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DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }
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def findScratchpadFromICache: Option[AddressSet] = dtim_adapter.map { s =>
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val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)
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@ -4,7 +4,7 @@
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package freechips.rocketchip.util
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import Chisel._
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import chisel3.experimental.{dontTouch, RawModule}
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import chisel3.experimental.{ChiselAnnotation, RawModule}
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import freechips.rocketchip.config.Parameters
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import scala.math._
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@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
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trait DontTouch {
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self: RawModule =>
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def dontTouch(data: Data): Unit = data match {
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case agg: Aggregate =>
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agg.getElements.foreach(dontTouch)
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case elt: Element =>
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annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
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}
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/** Marks every port as don't touch
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*
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* @note This method can only be called after the Module has been fully constructed
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@ -35,6 +42,11 @@ trait DontTouch {
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self.getModulePorts.foreach(dontTouch(_))
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self
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}
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def dontTouchPortsExcept(f: Data => Boolean): this.type = {
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self.getModulePorts.filterNot(f).foreach(dontTouch(_))
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self
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}
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}
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trait Clocked extends Bundle {
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