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util: dontTouch work-around for zero width aggregates

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This commit is contained in:
Henry Cook 2018-01-08 15:58:28 -08:00
parent b77b93b0b4
commit 5075a93e6c
1 changed files with 8 additions and 1 deletions
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9
src/main/scala/util/Misc.scala
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@ -4,7 +4,7 @@
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental.{dontTouch, RawModule}
import chisel3.experimental.{ChiselAnnotation, RawModule}
import freechips.rocketchip.config.Parameters
import scala.math._
@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
trait DontTouch {
self: RawModule =>
def dontTouch(data: Data): Unit = data match {
case agg: Aggregate =>
agg.getElements.foreach(dontTouch)
case elt: Element =>
annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
}
/** Marks every port as don't touch
*
* @note This method can only be called after the Module has been fully constructed