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Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) 

In accordance with https://github.com/freechipsproject/chisel3/issues/752
This commit is contained in:
pentin-as 2018-01-09 16:06:43 -05:00 committed by Andrew Waterman
parent 7fc8337cdb
commit c152962642
1 changed files with 4 additions and 3 deletions
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7
src/main/scala/rocket/HellaCache.scala
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@ -257,11 +257,12 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
val metabits = rstVal.getWidth
val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = metabits)))
when (rst || io.write.valid) {
val wen = rst || io.write.valid
when (wen) {
tag_array.write(waddr, Vec.fill(nWays)(wdata), wmask)
}
io.resp := tag_array.read(io.read.bits.idx, io.read.valid).map(rstVal.fromBits(_))
io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(rstVal.fromBits(_))
io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
io.read.ready := !wen // so really this could be a 6T RAM
io.write.ready := !rst
}