ResetCatchAndSync: work also in the context of a RawModule (#1202)
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@ -3,6 +3,7 @@
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package freechips.rocketchip.util
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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/** Reset: asynchronous assert,
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* synchronous de-assert
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@ -28,12 +29,12 @@ object ResetCatchAndSync {
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def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
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psd: Option[PSDTestMode] = None): Bool = {
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.clock := clk
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catcher.reset := rst
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catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
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catcher.io.sync_reset
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withClockAndReset(clk, rst) {
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val catcher = Module (new ResetCatchAndSync(sync))
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if (name.isDefined) {catcher.suggestName(name.get)}
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catcher.io.psd <> psd.getOrElse(Wire(new PSDTestMode()).fromBits(UInt(0)))
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catcher.io.sync_reset
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}
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}
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def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
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