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Merge pull request #1176 from freechipsproject/fix-tl-port 

Fix TL MMIO port
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Henry Cook 2018-01-05 20:37:44 -08:00 committed by GitHub
parent 3525489fff f749e986cf
commit 4fd4ae38e3
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1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Ports.scala
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@ -195,7 +195,7 @@ trait HasMasterTLMMIOPortBundle {
trait HasMasterTLMMIOPortModuleImp extends LazyModuleImp with HasMasterTLMMIOPortBundle {
val outer: HasMasterTLMMIOPort
val mmio_tl = IO(HeterogeneousBag.fromNode(outer.mmio_tl.in))
(mmio_tl zip outer.mmio_tl.out) foreach { case (i, (o, _)) => i <> o }
(mmio_tl zip outer.mmio_tl.in) foreach { case (i, (o, _)) => i <> o }
}
/** Adds an TL port to the system intended to be a slave on an MMIO device bus.