Let user of CSRFile decide when to set tval
I also renamed badaddr to tval (the correct name).
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@ -196,7 +196,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
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val retire = UInt(INPUT, log2Up(1+retireWidth))
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val cause = UInt(INPUT, xLen)
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val pc = UInt(INPUT, vaddrBitsExtended)
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val badaddr = UInt(INPUT, vaddrBitsExtended)
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val tval = UInt(INPUT, vaddrBitsExtended)
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val time = UInt(OUTPUT, xLen)
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val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
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val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
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@ -527,12 +527,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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assert(!reg_singleStepped || io.retire === UInt(0))
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val epc = formEPC(io.pc)
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val write_badaddr = exception && cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
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Causes.misaligned_load, Causes.misaligned_store,
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Causes.load_access, Causes.store_access, Causes.fetch_access,
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Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
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val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
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val noCause :: mCause :: hCause :: sCause :: uCause :: Nil = Enum(5)
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val xcause_dest = Wire(init = noCause)
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@ -549,7 +543,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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reg_sepc := epc
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reg_scause := cause
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xcause_dest := sCause
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reg_sbadaddr := badaddr_value
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reg_sbadaddr := io.tval
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reg_mstatus.spie := reg_mstatus.sie
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reg_mstatus.spp := reg_mstatus.prv
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reg_mstatus.sie := false
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@ -558,7 +552,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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reg_mepc := epc
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reg_mcause := cause
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xcause_dest := mCause
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reg_mbadaddr := badaddr_value
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reg_mbadaddr := io.tval
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reg_mstatus.mpie := reg_mstatus.mie
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reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
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reg_mstatus.mie := false
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@ -808,7 +802,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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t.priv := Cat(reg_debug, reg_mstatus.prv)
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t.cause := cause
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t.interrupt := cause(xLen-1)
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t.tval := badaddr_value
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t.tval := io.tval
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}
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def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {
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@ -545,7 +545,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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csr.io.fcsr_flags := io.fpu.fcsr_flags
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csr.io.rocc_interrupt := io.rocc.interrupt
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csr.io.pc := wb_reg_pc
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csr.io.badaddr := encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata)
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val tval_valid = wb_xcpt && wb_cause.isOneOf(Causes.illegal_instruction, Causes.breakpoint,
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Causes.misaligned_load, Causes.misaligned_store,
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Causes.load_access, Causes.store_access, Causes.fetch_access,
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Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
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csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
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io.ptw.ptbr := csr.io.ptbr
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io.ptw.status := csr.io.status
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io.ptw.pmp := csr.io.pmp
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