riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #1244 from freechipsproject/dtim-priority 

Give Rocket priority over DTIM TL port
This commit is contained in:
Andrew Waterman 2018-02-20 14:19:21 -08:00 committed by GitHub
parent db35f45bf7 1bac2cbdf8
commit 1b158d2caf
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/tile/RocketTile.scala
View File

@ -105,8 +105,6 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
val uncorrectable = RegInit(Bool(false))
val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(IO(Bool(OUTPUT)))
outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem }
outer.bus_error_unit.foreach { lm =>
lm.module.io.errors.dcache := outer.dcache.module.io.errors
lm.module.io.errors.icache := outer.frontend.module.io.errors
@ -130,6 +128,9 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
core.io.rocc.busy := roccCore.busy
core.io.rocc.interrupt := roccCore.interrupt
// Rocket has higher priority to DTIM than other TileLink clients
outer.dtim_adapter.foreach { lm => dcachePorts += lm.module.io.dmem }
when(!uncorrectable) { uncorrectable :=
List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
.flatMap { e => e.uncorrectable.map(_.valid) }