Yunsup Lee
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309193dd07
|
change llc size
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2012-07-24 14:10:29 -07:00 |
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Yunsup Lee
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6541cf22a4
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
|
Yunsup Lee
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f4e3e72ad1
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hoist HTIF_WIDTH out to consts
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2012-07-23 17:30:04 -07:00 |
|
Andrew Waterman
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a21c355114
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fix htif split request/response
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2012-07-23 17:15:16 -07:00 |
|
Andrew Waterman
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938effc053
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
|
Yunsup Lee
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379f021359
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change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
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2012-07-22 18:26:02 -07:00 |
|
Yunsup Lee
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c892950bf1
|
hoist out uncore as its own component
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2012-07-22 17:48:17 -07:00 |
|
Huy Vo
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0a97d6ab4d
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type casting
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2012-07-18 13:03:35 -07:00 |
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Andrew Waterman
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f42c6afed2
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Andrew Waterman
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
|
Yunsup Lee
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f633a55722
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fix dcache tag array size
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2012-07-16 22:19:03 -07:00 |
|
Andrew Waterman
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e496cd7584
|
use Mem to implement queues to speed things up
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2012-07-13 21:48:05 -07:00 |
|
Huy Vo
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fd95159837
|
INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
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bac82762d3
|
use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
|
Andrew Waterman
|
429fcbed8e
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
Andrew Waterman
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f645fb4dd7
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Andrew Waterman
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5035374f36
|
update to new chisel
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2012-07-08 17:59:41 -07:00 |
|
Andrew Waterman
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39d198ecdc
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fix htif handling of large memory reads
|
2012-06-26 19:12:11 -07:00 |
|
Andrew Waterman
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4e5f874266
|
update to new chisel/hwacha
|
2012-06-08 00:13:14 -07:00 |
|
Huy Vo
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a99cebb483
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
|
Huy Vo
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04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Huy Vo
|
c975c21e44
|
views removed
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
943b6d0616
|
remove debug println
|
2012-06-06 02:48:48 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Huy Vo
|
181b20d69c
|
working vec unit with pvfb
|
2012-05-24 10:38:14 -07:00 |
|
Andrew Waterman
|
faee45bf4c
|
fix setpcr/clearpcr not writing rd
|
2012-05-21 07:25:35 -07:00 |
|
Yunsup Lee
|
c9602a0d2e
|
fix vector control decode bug
|
2012-05-15 10:26:37 -07:00 |
|
Gage W Eads
|
d0bc995c88
|
Fixed IRQ_IPI -> IRQ_TIMER typo
|
2012-05-14 22:25:12 -07:00 |
|
Andrew Waterman
|
a2f6d01c1b
|
add programmable coreid register
|
2012-05-09 03:09:22 -07:00 |
|
Andrew Waterman
|
e0e1cd5d32
|
add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
|
2012-05-08 22:58:00 -07:00 |
|
Henry Cook
|
87cbae2c8a
|
Removed defunct ioDmem
|
2012-05-07 17:31:39 -07:00 |
|
Andrew Waterman
|
b851f1b34c
|
support maximum-MTU HTIF packets
|
2012-05-03 21:11:43 -07:00 |
|
Andrew Waterman
|
171c87002e
|
reduce HTIF clock divider for now
|
2012-05-03 04:21:11 -07:00 |
|
Andrew Waterman
|
e1f9dc2c1f
|
generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
|
2012-05-03 02:29:09 -07:00 |
|
Andrew Waterman
|
2d4e5d3813
|
fix pseudo-LRU verilog generation bug
|
2012-05-02 19:31:31 -07:00 |
|
Henry Cook
|
622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
|
65ff397122
|
improved instruction decoding
it now makes use of don't-cares by performing logic minimization
|
2012-05-01 20:16:36 -07:00 |
|
Andrew Waterman
|
4cfa6cd9a8
|
force Top.main's return type to Unit
|
2012-05-01 19:55:16 -07:00 |
|
Andrew Waterman
|
5819beed64
|
use parameterized FP units
|
2012-05-01 01:25:43 -07:00 |
|
Andrew Waterman
|
eafdffe125
|
simplify page table walker; speed up emulator
|
2012-05-01 01:24:36 -07:00 |
|
Andrew Waterman
|
c13d3e6f88
|
fix probe tag read-modify-write atomicity violation
|
2012-04-26 02:29:31 -07:00 |
|
Andrew Waterman
|
66f86a2194
|
use pseudo-LRU replacement for TLBs
|
2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
a0378c5d2f
|
remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
|
2012-04-26 02:29:30 -07:00 |
|
Andrew Waterman
|
6d8fc74378
|
fix DTLB permissions bug
|
2012-04-26 02:29:30 -07:00 |
|
Henry Cook
|
1ed89f1cab
|
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
|
2012-04-24 17:17:42 -07:00 |
|
Henry Cook
|
55e86b5cf4
|
Fixed coherence bug: probe counting for single tile
|
2012-04-24 17:17:13 -07:00 |
|
Henry Cook
|
a39080d0b1
|
Fixed abort bug: xact_abort.ready was not pinned high
|
2012-04-24 17:16:40 -07:00 |
|
Andrew Waterman
|
fb4408b150
|
fix AMO replay/coherence deadlock
|
2012-04-15 22:56:02 -07:00 |
|
Andrew Waterman
|
724735f13f
|
fix writeback bug
|
2012-04-13 03:16:48 -07:00 |
|