Henry Cook
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a7fa77c7fc
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track operand size for Gets
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2015-05-13 23:28:18 -07:00 |
|
Henry Cook
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172c372d3e
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L2 alloc cleanup
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2015-05-12 17:14:06 -07:00 |
|
Henry Cook
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5fdae2cb61
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Merge branch 'master' of github.com:ucb-bar/uncore
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2015-05-07 16:18:23 -07:00 |
|
Henry Cook
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fc883b5049
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rm index.html
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2015-05-07 16:17:40 -07:00 |
|
Henry Cook
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8362eba00f
|
Merge branch 'gh-pages'
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2015-05-07 16:16:13 -07:00 |
|
Henry Cook
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aec24cf1a7
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readme
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2015-05-07 16:16:07 -07:00 |
|
Henry Cook
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62b6f24798
|
Delete TileLink0.3.1Specification.pdf
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2015-05-07 15:43:06 -07:00 |
|
Henry Cook
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90ced93eeb
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Merge branch 'master' into gh-pages
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2015-05-07 12:35:14 -07:00 |
|
Henry Cook
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4cef8c9cd4
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Added MemIOArbiter
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2015-05-07 10:55:38 -07:00 |
|
Christopher Celio
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b09832f1b5
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ICache now returns the "next PC" signal.
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
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2015-05-07 04:53:05 -07:00 |
|
Colin Schmidt
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c746ef8702
|
fix bug in rocc port resp for FPtoInt instructions
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2015-05-04 11:20:55 -07:00 |
|
Henry Cook
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8832b454ce
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add plugins to make scala doc site and publish to ghpages
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2015-04-29 15:34:56 -07:00 |
|
Henry Cook
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1e05fc0525
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First pages commit
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2015-04-29 13:18:26 -07:00 |
|
Yunsup Lee
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b9fb1bb46e
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port
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2015-04-29 00:43:53 -07:00 |
|
Henry Cook
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3673295d03
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network shim cleanup
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2015-04-27 16:59:30 -07:00 |
|
Henry Cook
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09e30041ed
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Voluntary Writeback tracker rewrite
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2015-04-27 12:56:33 -07:00 |
|
Colin Schmidt
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a37fad2e9b
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Merge branch 'retimeable-frontend' into rocc-fpu-port
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2015-04-22 14:23:52 -07:00 |
|
Colin Schmidt
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1f410ac42c
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move fetch buffer into frontend to allow retiming
|
2015-04-22 11:26:03 -07:00 |
|
Henry Cook
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11b5222d01
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Refactored WritebackUnit
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2015-04-21 22:23:04 -07:00 |
|
Henry Cook
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4c7969b2b3
|
Metadata docs and api cleanup
|
2015-04-20 16:32:09 -07:00 |
|
Henry Cook
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a315fe93c1
|
simplify ClientMetadata.makeRelease
|
2015-04-20 10:46:24 -07:00 |
|
Henry Cook
|
f66a9fd7a6
|
simplify ClientMetadata.makeRelease
|
2015-04-20 10:46:02 -07:00 |
|
Henry Cook
|
6d40a61060
|
TileLink scala doc and parameter renaming
|
2015-04-19 22:06:44 -07:00 |
|
Albert Ou
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ca5b3d988d
|
Merge branch 'master' into rocc-fpu-port
|
2015-04-19 15:00:00 -07:00 |
|
Henry Cook
|
3048f4785a
|
HeaderlessTileLinkIO -> ClientTileLinkIO
|
2015-04-17 16:56:53 -07:00 |
|
Henry Cook
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ba7a8b1752
|
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
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2015-04-17 16:55:20 -07:00 |
|
Colin Schmidt
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73fa28521d
|
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
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2015-04-16 15:22:08 -07:00 |
|
Henry Cook
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ce3271aef2
|
refactor LNClients and LNManagers
|
2015-04-15 15:48:36 -07:00 |
|
Henry Cook
|
49f1c0aa7b
|
moved ecc lib to uncore
|
2015-04-13 15:58:10 -07:00 |
|
Henry Cook
|
91e882e3f8
|
Use HeaderlessTileLinkIO
|
2015-04-13 15:58:10 -07:00 |
|
Henry Cook
|
90f800d87d
|
Grant bugfixes and more comments
|
2015-04-13 15:57:06 -07:00 |
|
Andrew Waterman
|
24bb032ede
|
Merge pull request #7 from ccelio/master
Rocket front-end can now fetch 4 instructions; added assert to dcache; refactoring
|
2015-04-12 19:18:23 -07:00 |
|
Christopher Celio
|
517d0d4b89
|
feedback on PR
|
2015-04-12 18:44:03 -07:00 |
|
Christopher Celio
|
4d6ebded02
|
Added assert to nbdcache
|
2015-04-11 02:58:34 -07:00 |
|
Christopher Celio
|
a564f08702
|
Rename dmem.sret signal to more accurate invalidate_lr
|
2015-04-11 02:26:33 -07:00 |
|
Christopher Celio
|
8fc2d38ca9
|
Removed unnecessary signal in CSRIO
|
2015-04-11 02:20:34 -07:00 |
|
Christopher Celio
|
2f88c5ca9d
|
Renamed PCR to CSR
|
2015-04-11 02:16:44 -07:00 |
|
Christopher Celio
|
11dbd4221a
|
Fixed front-end to support four-wide fetch.
|
2015-04-10 17:53:47 -07:00 |
|
Colin Schmidt
|
bd72db92c1
|
update rocc port to use fdiv/sqrt
|
2015-04-07 15:02:02 -07:00 |
|
Amirali Sharifian
|
879a4a0bcd
|
Update Makefile
Change default shell to bash shell.
|
2015-04-06 15:05:43 -07:00 |
|
Colin Schmidt
|
887a8de189
|
Merge branch 'master' of github.com:ucb-bar/rocket into rocc-fpu-port
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2015-04-06 13:48:44 -07:00 |
|
Henry Cook
|
3cf1778c92
|
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
|
2015-04-06 12:22:23 -07:00 |
|
Henry Cook
|
9708d25dff
|
Restructure L2 state machine and utilize HeaderlessTileLinkIO
|
2015-04-06 12:19:51 -07:00 |
|
Andrew Waterman
|
9ade0e41cc
|
Integrate divide/sqrt unit
|
2015-04-04 16:39:17 -07:00 |
|
Andrew Waterman
|
fe27b9b1b2
|
Support writing sstatus.fs even without an FPU
|
2015-04-04 15:20:18 -07:00 |
|
Andrew Waterman
|
bce62d5774
|
Update PTE format to reflect reserved bits
|
2015-04-04 15:19:15 -07:00 |
|
Colin Schmidt
|
a369d8f17f
|
Add fpu port to the rocc interface
|
2015-04-02 01:30:11 -07:00 |
|
Henry Cook
|
ced627f00a
|
slight mod to pending_puts
cleaner state transition logic
|
2015-04-01 15:24:53 -07:00 |
|
Andrew Waterman
|
c941f0a68e
|
New virtual memory implementation (Sv39)
|
2015-03-27 16:21:29 -07:00 |
|
Andrew Waterman
|
d912ea265e
|
New virtual memory implementation (Sv39)
|
2015-03-27 16:20:59 -07:00 |
|