efc6c9cbd3
Let user of CSRFile decide when to set tval
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I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
a59fc3bdaa
Teach MulDiv to do either mul-only or div-only by setting unroll=0
2018-02-06 14:03:17 -08:00
69441930b5
Rationalize ALU function encoding
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MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
c1eb795aba
move sbt-launch to match project/build.properties ( #1222 )
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therefore *everything* is now 1.0.4
2018-02-02 17:13:05 -08:00
e26363a176
Don't pass deprecated -ffaaf option to firrtl ( #1221 )
2018-02-01 14:46:38 -08:00
18e3bf3701
Bump Firrtl ( #1219 )
2018-01-31 14:31:54 -08:00
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
ad58b37437
Merge pull request #1215 from freechipsproject/config-altermap
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Misc updates to Config and Generator APIs
2018-01-31 14:22:17 -08:00
b1fa19e801
bump hardfloat for scala 2.11.12 ( #1216 )
2018-01-30 20:42:36 -08:00
7dad486707
util: updates to internal Generator API
2018-01-30 15:19:37 -08:00
bd50a1a4bc
config: remove deprecated Parameters.root
2018-01-30 11:52:44 -08:00
46751bedeb
config: MapParameters are back in style
2018-01-30 11:52:44 -08:00
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
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Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
a749326deb
Add cover points to registers ( #1208 )
2018-01-24 21:37:24 -08:00
94d2edceb9
Merge pull request #1205 from freechipsproject/fpu-cover
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Add some covers for VM and FPU
2018-01-23 18:49:45 -08:00
7a0252fdfc
Add some covers for FPU structural hazards
2018-01-23 16:32:03 -08:00
a2ca82f92c
Add VM covers
2018-01-23 16:13:35 -08:00
dcda98dcaf
Disable coverage collection for testbench related verilog files ( #1204 )
2018-01-22 16:40:38 -08:00
c32150b994
ResetCatchAndSync: work also in the context of a RawModule ( #1202 )
2018-01-19 19:45:52 -08:00
f6f5606f8e
diplomacy: run user instantiate() method after nodes are initialized ( #1198 )
2018-01-18 14:57:47 -08:00
5cc1411e14
Merge pull request #1199 from freechipsproject/require-messages
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rocket: add address to tlb permissions require msgs
2018-01-18 14:53:25 -08:00
bf5dd6dac3
Replace Parameters in cover with globally setable implementation ( #1200 )
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This change is made in anticipation of a proper coverage library
2018-01-18 14:45:36 -08:00
24c1235500
rocket: add address to tlb permissions require msgs
2018-01-18 10:31:51 -08:00
5854fb5f7c
SourceShrinker improvements ( #1197 )
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* SourceShrinker: preserve FIFO guarantees of slaves
* tilelink: document that Releases can use TtoT, BtoB, and NtoN
TtoT is needed for write-through caches.
2018-01-17 18:02:19 -08:00
338e453a91
JTAG: Use new withClock way of overriding clocks ( #1072 )
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* JTAG: Use new withClock way of overriding clocks
the override clock way is deprecated
* JTAG: use withClock instead of override clock
* JTAG: extend Module for ClockedCounter
* JTAG: Don't use deprecated clock constructs
* JTAG: Remove another override_clock
* Rename "NegativeEdgeLatch"
because it's not a latch, it's just a register on the negative edge of the clock.
* Use the appropriately named NegEdgeReg
* JTAG: Rename another NegativeEdgeLatch
2018-01-17 13:59:05 -08:00
80ca018e3a
Add cover points for BusErrorUnit ( #1193 )
2018-01-15 18:00:29 -08:00
6c6afc5bc9
Merge pull request #1191 from edcote/patch-2
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remove string type ambiguity in header
2018-01-15 13:33:27 -08:00
ff11673a9c
remove string type ambiguity in header
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I ran into a compilation issue.
This link explains the problem well: https://stackoverflow.com/a/5499222/3736700
For example, in a header file, it is generally not considered a good idea to put the line using namespace std; (or to use any namespace, for that matter) because it can cause names in files that include that header to become ambiguous. In this setup, you would just #include <string> in the header, then use std::string to refer to the string type.
2018-01-13 13:29:22 -08:00
8799508b1f
Merge pull request #1179 from freechipsproject/refactored_rbb
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Add Debug tests to Regressions
2018-01-12 10:34:48 -08:00
b8219425d8
Fix spelling and capitalization in README.md ( #1182 )
2018-01-10 15:52:07 -08:00
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
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Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
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In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
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Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
a530646d15
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-08 09:11:27 -08:00
4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port
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Fix TL MMIO port
2018-01-05 20:37:44 -08:00
3525489fff
Merge pull request #1174 from freechipsproject/error-device-tracked
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Claim that ErrorDevice is TRACKED
2018-01-05 17:17:22 -08:00
427b6c9ab8
Emulator: Update it to allow some hard-coded Verilog PlusArgs
2018-01-05 17:08:21 -08:00
76c5fd0c0c
travis: Use newer infrastructure, but require sudo for additional disk space.
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This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
2018-01-05 17:08:21 -08:00
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
b643f3dca6
debug regressions: some whitespace and null ptr cleanup
2018-01-05 17:08:21 -08:00
96dd5d8c38
Emulator example clarifications
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-05 17:08:21 -08:00
7ae6bf7611
Arguments clarification, add examples
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This clarifies and provides consistent for the command line arguments
usage text.
This adds a set of examples for running the rocket-chip emulator.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com >
2018-01-05 17:08:21 -08:00
1aa87f6578
Make emulator.cc understand HTIF arguments
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This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
