riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,472 Commits 1 Branch 0 Tags
db76ff2d8689f96ba344106d3f07915755f4305b
Commit Graph

4472 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Henry Cook
cb5ce3fe73 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
4ebf637642 More broadcast hub bugfixes 2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187 fix icache prefetch global_xact_id bug 2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d going back to null coherence hub 2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman
d777f1cb24 fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Andrew Waterman
4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f vector exception handler now handles prefetches correctly 2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91 Fixed global_xact_id propagation bug 2012-03-09 11:05:44 -08:00
Henry Cook
2014db41bd Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Henry Cook
9319130483 Special cased NTILES == 1 due to log2up revision 2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman
2607153b67 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman
3a72ace057 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman
ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd major refactoring on vector exception interface 2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53 change how fence.*.cv works, now control processor stalls on the fence instruction 2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646 icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data 2012-03-08 18:47:32 -08:00
Henry Cook
2df5c19f13 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
4d2e7172f6 Added require_ack field to TransactionReply bundle 2012-03-08 18:07:44 -08:00
Henry Cook
ca5caf898c Hub addr comparison bug fix 2012-03-08 16:39:05 -08:00
Henry Cook
35c4bd4084 Hub addr comparison bug fix 2012-03-08 16:39:05 -08:00
Henry Cook
3fc94d627d Fixed dependency queue bug in Broadcast Hub 2012-03-08 11:36:10 -08:00
Henry Cook
788ad327da Fixed dependency queue bug in Broadcast Hub 2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9 PriorityEncoder apply() no longer has recursive depth param 2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman
df6ac34821 coherence hub fixes 2012-03-07 21:03:44 -08:00
Andrew Waterman
941873bad1 coherence hub fixes 2012-03-07 21:03:44 -08:00
Henry Cook
1a90e2a162 Broadcast hub bug fixes for load uncached mem req and store uncached xact rep 2012-03-07 11:40:49 -08:00
Henry Cook
7deff5fbe2 Broadcast hub bug fixes for load uncached mem req and store uncached xact rep 2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman
7929600874 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman
a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman
6e2610b0ad fix Mux1H for bundles 2012-03-06 23:38:36 -08:00
Yunsup Lee
81dcb194d3 new vector exception interface 2012-03-06 22:39:15 -08:00
Henry Cook
35ffb80911 unified coherence trait functions 2012-03-06 17:33:11 -08:00
Henry Cook
47a2097507 unified coherence trait functions 2012-03-06 17:33:11 -08:00
Henry Cook
1e02618cc8 hub code cleanup 2012-03-06 17:01:47 -08:00
Henry Cook
3dd404dcf4 hub code cleanup 2012-03-06 17:01:47 -08:00
Henry Cook
762f2551a7 newTransactionOnMiss() 2012-03-06 15:54:41 -08:00
Henry Cook
c0ed010bc9 newTransactionOnMiss() 2012-03-06 15:54:41 -08:00
Henry Cook
3874da4a4f Added store dependency queues to BroadcastHub. Minor improvements to utils. 2012-03-06 15:54:41 -08:00
Henry Cook
962e5a54af Added store dependency queues to BroadcastHub. Minor improvements to utils. 2012-03-06 15:54:41 -08:00
Andrew Waterman
499c5b4a2e automatically infer MEM_TAG_BITS 2012-03-06 15:49:28 -08:00
Andrew Waterman
012b991ffe implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman
6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00
Yunsup Lee
dba99e07a9 set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4 2012-03-06 08:54:21 -08:00