hub code cleanup
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762f2551a7
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1e02618cc8
@ -141,6 +141,9 @@ trait FourStateCoherence extends CoherencePolicy {
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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}
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//TODO: do we need isPresent() for determining that a line needs to be
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//upgraded but that no replacement is needed?
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def isValid (state: UFix): Bool = {
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state != tileInvalid
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}
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@ -224,8 +227,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_p_rep_dep = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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val pop_x_init_data = Bool(OUTPUT)
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val pop_x_init = Bits(NTILES, OUTPUT)
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val pop_x_init_data = Bits(NTILES, OUTPUT)
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val pop_x_init_dep = Bits(NTILES, OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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@ -247,7 +250,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, pop_data: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) {
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
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req_cmd.valid := !cmd_sent && at_front_of_dep_queue
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req_cmd.bits.rw := Bool(true)
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req_data.valid := data.valid && at_front_of_dep_queue
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@ -257,11 +260,11 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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cmd_sent := Bool(true)
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}
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when(req_data.ready && req_data.valid) {
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pop_data := Bool(true)
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pop_data := UFix(1) << tile_id
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mem_cnt := mem_cnt_next
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}
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when(mem_cnt_next === UFix(0)) {
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pop_dep := Bool(true)
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pop_dep := UFix(1) << tile_id
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trigger := Bool(false)
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}
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}
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@ -315,8 +318,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.pop_p_rep := Bits(0, width = NTILES)
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io.pop_p_rep_data := Bits(0, width = NTILES)
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io.pop_p_rep_dep := Bits(0, width = NTILES)
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io.pop_x_init := Bool(false)
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io.pop_x_init_data := Bool(false)
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io.pop_x_init := Bits(0, width = NTILES)
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io.pop_x_init_data := Bits(0, width = NTILES)
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io.pop_x_init_dep := Bits(0, width = NTILES)
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io.send_x_rep_ack := Bool(false)
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@ -334,7 +337,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_x_init := Bool(true)
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io.pop_x_init := UFix(1) << io.alloc_req.bits.tile_id
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state := Mux(p_req_flags.orR, s_probe, s_mem)
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}
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}
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@ -367,20 +370,22 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.mem_req_lock,
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io.p_rep_data,
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p_rep_data_needs_write,
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io.pop_p_rep_data,
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p_w_mem_cmd_sent,
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io.pop_p_rep_data,
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io.pop_p_rep_dep,
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io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.global_xact_id === UFix(id)))
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io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.global_xact_id === UFix(id)),
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p_rep_tile_id_)
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} . elsewhen(x_init_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.x_init_data,
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x_init_data_needs_write,
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io.pop_x_init_data,
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x_w_mem_cmd_sent,
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io.pop_x_init_data,
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io.pop_x_init_dep,
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io.x_init_data_dep.valid && (io.x_init_data_dep.bits.global_xact_id === UFix(id)))
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io.x_init_data_dep.valid && (io.x_init_data_dep.bits.global_xact_id === UFix(id)),
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init_tile_id_)
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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@ -625,23 +630,23 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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trackerList(i).io.x_init_data.bits := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.bits
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trackerList(i).io.x_init_data.valid := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.valid
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//TODO trackerList(i).io.x_init_data_dep <> x_init_data_dep_arr(trackerList(i).io.init_tile_id)
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trackerList(i).io.x_init_data_dep.bits <> MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
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trackerList(i).io.x_init_data_dep.bits := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
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trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.valid, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid))
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}
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for( j <- 0 until NTILES ) {
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val x_init = io.tiles(j).xact_init
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val x_init_data = io.tiles(j).xact_init_data
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val x_init_data_dep = x_init_data_dep_list(j).io.deq
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init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && x_init.valid
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init_arb.io.in(j).bits.xact_init := x_init.bits
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init_arb.io.in(j).bits.tile_id := UFix(j)
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val pop_x_inits = trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.tile_id === UFix(j))
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val pop_x_inits = trackerList.map(_.io.pop_x_init(j).toBool)
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val do_pop = foldR(pop_x_inits)(_||_)
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x_init_data_dep_list(j).io.enq.valid := do_pop
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x_init_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_x_inits)
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x_init.ready := (abort_state_arr(j) === s_abort_complete) || do_pop
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x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.tile_id === UFix(j)))(_||_)
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x_init_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_x_init_dep(j).toBool))(_||_)
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x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data(j).toBool))(_||_)
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x_init_data_dep.ready := foldR(trackerList.map(_.io.pop_x_init_dep(j).toBool))(_||_)
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}
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alloc_arb.io.out.ready := init_arb.io.out.valid
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