unified coherence trait functions
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@ -126,7 +126,15 @@ trait ThreeStateIncoherence extends CoherencePolicy {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, state)
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}
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def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = X_INIT_READ_EXCLUSIVE
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def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, tileClean)
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}
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def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = state
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.t_type != X_INIT_WRITE_UNCACHED)
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}
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trait FourStateCoherence extends CoherencePolicy {
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@ -162,7 +170,7 @@ trait FourStateCoherence extends CoherencePolicy {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_REP_READ_SHARED -> tileShared,
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X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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