change D$ to use FourStateCoherence protocol
instead of ThreeStateIncoherence.
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parent
35ffb80911
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7929600874
@ -121,17 +121,18 @@ trait ThreeStateIncoherence extends CoherencePolicy {
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Mux(write, tileDirty, Mux(read, Mux(state === tileDirty, tileDirty, tileClean), state))
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}
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def newStateOnHit(cmd: Bits, state: UFix): UFix = newState(cmd, state)
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def newStateOnPrimaryMiss(cmd: Bits): UFix = newState(cmd, tileInvalid)
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix = {
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def newTransactionOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, state)
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Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = X_INIT_READ_EXCLUSIVE
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def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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def newTransactionOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileDirty, tileClean)
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}
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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}
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def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = Bool(false)
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def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileDirty, tileClean)
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}
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def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = state
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.t_type != X_INIT_WRITE_UNCACHED)
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@ -166,11 +167,20 @@ trait FourStateCoherence extends CoherencePolicy {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileExclusiveDirty, state)
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}
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def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = {
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def newTransactionOnPrimaryMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def newStateOnTransactionRep(cmd: Bits, incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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def newTransactionOnSecondaryMiss(cmd: Bits, state: UFix, outstanding: TransactionInit): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, outstanding.t_type)
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}
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def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
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}
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def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_REP_READ_SHARED -> tileShared,
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X_REP_READ_EXCLUSIVE -> Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileExclusiveDirty, tileExclusiveClean),
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@ -179,11 +189,6 @@ trait FourStateCoherence extends CoherencePolicy {
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X_REP_WRITE_UNCACHED -> tileInvalid
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))
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}
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def needsSecondaryXact(cmd: Bits, outstanding: TransactionInit): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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(read && (outstanding.t_type === X_INIT_READ_UNCACHED || outstanding.t_type === X_INIT_WRITE_UNCACHED)) ||
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(write && (outstanding.t_type != X_INIT_READ_EXCLUSIVE))
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}
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def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = {
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MuxLookup(incoming.p_type, state, Array(
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