riscv/rocket-chip
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More broadcast hub bugfixes

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This commit is contained in:
Henry Cook 2012-03-11 14:17:27 -07:00
parent a4d0025187
commit 4ebf637642
2 changed files with 32 additions and 38 deletions
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15
rocket/src/main/scala/coherence.scala
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@ -276,17 +276,17 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
when(req_data.ready && req_data.valid) {
pop_data := UFix(1) << tile_id
mem_cnt := mem_cnt_next
}
when(mem_cnt_next === UFix(0)) {
pop_dep := UFix(1) << tile_id
trigger := Bool(false)
when(mem_cnt_next === UFix(0)) {
pop_dep := UFix(1) << tile_id
trigger := Bool(false)
}
}
}
def doMemReqRead(req_cmd: ioDecoupled[MemReqCmd], trigger: Bool) {
req_cmd.valid := Bool(true)
req_cmd.bits.rw := Bool(false)
when(req_cmd.ready ) {
when(req_cmd.ready) {
trigger := Bool(false)
}
}
@ -535,10 +535,11 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
rep.bits.t_type := getTransactionReplyType(t_type_arr(ack_idx), sh_count_arr(ack_idx))
rep.bits.tile_xact_id := tile_xact_id_arr(ack_idx)
rep.bits.global_xact_id := ack_idx
rep.valid := (UFix(j) === init_tile_id_arr(ack_idx)) && send_x_rep_ack_arr.toBits.orR
val do_send_ack = (UFix(j) === init_tile_id_arr(ack_idx)) && send_x_rep_ack_arr.toBits.orR
rep.valid := do_send_ack
sent_x_rep_ack_arr(ack_idx) := do_send_ack
}
}
sent_x_rep_ack_arr(ack_idx) := !io.mem.resp.valid
// If there were a ready signal due to e.g. intervening network use:
//io.mem.resp.ready := io.tiles(init_tile_id_arr.read(mem_idx)).xact_rep.ready

55
rocket/src/main/scala/util.scala
View File

@ -194,40 +194,33 @@ class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {
val io = new ioLockingArbiter(n)(data)
val locked = Vec(n) { Reg(resetVal = Bool(false)) }
var dout = io.in(0).bits
var vout = Bool(false)
for (i <- 0 until n) {
io.in(i).ready := io.out.ready
}
val any_lock_held = (locked.toBits & io.lock.toBits).orR
when(any_lock_held) {
vout = io.in(0).valid && locked(0)
for (i <- 0 until n) {
io.in(i).ready := io.out.ready && locked(i)
dout = Mux(locked(i), io.in(i).bits, dout)
vout = vout || io.in(i).valid && locked(i)
}
} .otherwise {
io.in(0).ready := io.out.ready
locked(0) := io.out.ready && io.lock(0)
for (i <- 1 until n) {
io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
locked(i) := !io.in(i-1).valid && io.in(i-1).ready && io.lock(i)
}
dout = io.in(n-1).bits
for (i <- 1 until n)
dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
vout = io.in(0).valid
for (i <- 1 until n)
vout = vout || io.in(i).valid
val valid_arr = Vec(n) { Wire() { Bool() } }
val bits_arr = Vec(n) { Wire() { data } }
for(i <- 0 until n) {
valid_arr(i) := io.in(i).valid
bits_arr(i) := io.in(i).bits
}
vout <> io.out.valid
dout <> io.out.bits
io.in(0).ready := Mux(any_lock_held, io.out.ready && locked(0), io.out.ready)
locked(0) := Mux(any_lock_held, locked(0), io.in(0).ready && io.lock(0))
for (i <- 1 until n) {
io.in(i).ready := Mux(any_lock_held, io.out.ready && locked(i),
!io.in(i-1).valid && io.in(i-1).ready)
locked(i) := Mux(any_lock_held, locked(i), io.in(i).ready)
}
var dout = io.in(n-1).bits
for (i <- 1 until n)
dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
var vout = io.in(0).valid
for (i <- 1 until n)
vout = vout || io.in(i).valid
val lock_idx = PriorityEncoder(locked.toBits)
io.out.valid := Mux(any_lock_held, valid_arr(lock_idx), vout)
io.out.bits := Mux(any_lock_held, bits_arr(lock_idx), dout)
}
object PriorityEncoder