newTransactionOnMiss()
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@ -155,6 +155,10 @@ trait FourStateCoherence extends CoherencePolicy {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, tileExclusiveDirty, state)
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}
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def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = {
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val (read, write) = cpuCmdToRW(cmd)
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Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
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}
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def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
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MuxLookup(incoming.t_type, tileInvalid, Array(
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X_REP_READ_SHARED -> tileShared,
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