riscv/rocket-chip
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set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4

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Yunsup Lee 2012-03-06 08:54:21 -08:00
parent 5f33ab24b0
commit dba99e07a9
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/consts.scala
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@ -217,7 +217,7 @@ object Constants
val P_REP_COPY_ACK = UFix(5, P_REP_TYPE_BITS)
// external memory interface
val MEM_TAG_BITS = 4
val MEM_TAG_BITS = if (HAVE_VEC) 5 else 4
val MEM_DATA_BITS = 128
val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
require(MEM_TAG_BITS >= max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS))