riscv/rocket-chip
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newTransactionOnMiss()

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This commit is contained in:
Henry Cook 2012-03-06 15:54:19 -08:00
parent 962e5a54af
commit c0ed010bc9
1 changed files with 4 additions and 0 deletions
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4
rocket/src/main/scala/coherence.scala
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@ -155,6 +155,10 @@ trait FourStateCoherence extends CoherencePolicy {
val (read, write) = cpuCmdToRW(cmd)
Mux(write, tileExclusiveDirty, state)
}
def newTransactionOnMiss(cmd: Bits, state: UFix): UFix = {
val (read, write) = cpuCmdToRW(cmd)
Mux(write, X_INIT_READ_EXCLUSIVE, X_INIT_READ_SHARED)
}
def newStateOnTransactionRep(incoming: TransactionReply, outstanding: TransactionInit): UFix = {
MuxLookup(incoming.t_type, tileInvalid, Array(
X_REP_READ_SHARED -> tileShared,