Special cased NTILES == 1 due to log2up revision
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parent
3a72ace057
commit
2014db41bd
@ -297,7 +297,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_rep_count = if (NTILES == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = Bits(0, width = NTILES))
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val p_rep_tile_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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@ -346,7 +346,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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p_rep_count := UFix(NTILES-1)
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if(NTILES > 1) p_rep_count := UFix(NTILES-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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@ -366,7 +366,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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when(io.p_rep_cnt_dec.orR) {
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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io.pop_p_rep := io.p_rep_cnt_dec
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p_rep_count := p_rep_count_next
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if(NTILES > 1) p_rep_count := p_rep_count_next
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when(p_rep_count === UFix(0)) {
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io.pop_p_rep := Bool(true)
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state := s_mem
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