Added store dependency queues to BroadcastHub. Minor improvements to utils.
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@ -35,6 +35,9 @@ class TrackerAllocReq extends Bundle {
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val tile_id = Bits(width = TILE_ID_BITS)
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}
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class TrackerDependency extends Bundle {
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionInit extends Bundle {
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val t_type = Bits(width = X_INIT_TYPE_BITS)
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@ -196,9 +199,11 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val xact_finish = Bool(INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val p_rep_data = (new ioDecoupled) { new ProbeReplyData }.flip
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val x_init_data = (new ioDecoupled) { new TransactionInitData }.flip
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val p_rep_data = (new ioPipe) { new ProbeReplyData }.flip
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val x_init_data = (new ioPipe) { new TransactionInitData }.flip
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val sent_x_rep_ack = Bool(INPUT)
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val p_rep_data_dep = (new ioPipe) { new TrackerDependency }.flip
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val x_init_data_dep = (new ioPipe) { new TrackerDependency }.flip
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val mem_req_cmd = (new ioDecoupled) { new MemReqCmd }
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val mem_req_data = (new ioDecoupled) { new MemData }
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@ -214,8 +219,10 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_p_rep_dep = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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val pop_x_init_data = Bool(OUTPUT)
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val pop_x_init_dep = Bits(NTILES, OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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@ -236,13 +243,12 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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(t_type === X_INIT_WRITE_UNCACHED)
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}
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioDecoupled[MemData], trigger: Bool, pop_data: Bool, cmd_sent: Bool) {
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req_cmd.valid := !cmd_sent
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def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, pop_data: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) {
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req_cmd.valid := !cmd_sent && at_front_of_dep_queue
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req_cmd.bits.rw := Bool(true)
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data.ready := req_data.ready
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req_data.valid := data.valid && at_front_of_dep_queue
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req_data.bits := data.bits
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req_data.valid := data.valid
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lock := Bool(true)
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lock := at_front_of_dep_queue
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when(req_cmd.ready && req_cmd.valid) {
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cmd_sent := Bool(true)
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}
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@ -250,7 +256,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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pop_data := Bool(true)
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mem_cnt := mem_cnt_next
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}
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when(mem_cnt === ~UFix(0)) {
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when(mem_cnt_next === UFix(0)) {
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pop_dep := Bool(true)
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trigger := Bool(false)
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}
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}
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@ -277,7 +284,6 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2up(REFILL_CYCLES))
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@ -285,6 +291,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.busy := state != s_idle
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io.addr := addr_
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io.init_tile_id := init_tile_id_
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io.p_rep_tile_id := p_rep_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.t_type := t_type_
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@ -303,11 +310,11 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.push_p_req := Bits(0, width = NTILES)
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io.pop_p_rep := Bits(0, width = NTILES)
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io.pop_p_rep_data := Bits(0, width = NTILES)
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io.pop_p_rep_dep := Bits(0, width = NTILES)
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io.pop_x_init := Bool(false)
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io.pop_x_init_data := Bool(false)
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io.pop_x_init_dep := Bits(0, width = NTILES)
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io.send_x_rep_ack := Bool(false)
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io.x_init_data.ready := Bool(false) // don't care
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io.p_rep_data.ready := Bool(false) // don't care
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switch (state) {
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is(s_idle) {
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@ -321,7 +328,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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p_rep_count := UFix(NTILES-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id )
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mem_cnt := UFix(0)
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mem_cmd_sent := Bool(false)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.pop_x_init := Bool(true)
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state := Mux(p_req_flags.orR, s_probe, s_mem)
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}
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@ -350,9 +358,25 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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}
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is(s_mem) {
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when (p_rep_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.p_rep_data, p_rep_data_needs_write, io.pop_p_rep_data, p_w_mem_cmd_sent)
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.p_rep_data,
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p_rep_data_needs_write,
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io.pop_p_rep_data,
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p_w_mem_cmd_sent,
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io.pop_p_rep_dep,
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io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.global_xact_id === UFix(id)))
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} . elsewhen(x_init_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd, io.mem_req_data, io.mem_req_lock, io.x_init_data, x_init_data_needs_write, io.pop_x_init_data, x_w_mem_cmd_sent)
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.x_init_data,
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x_init_data_needs_write,
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io.pop_x_init_data,
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x_w_mem_cmd_sent,
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io.pop_x_init_dep,
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io.x_init_data_dep.valid && (io.x_init_data_dep.bits.global_xact_id === UFix(id)))
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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@ -457,6 +481,9 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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}
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}
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val p_rep_data_dep_list = List.fill(NTILES)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth must >= NPRIMARY
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val x_init_data_dep_list = List.fill(NTILES)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth should >= NPRIMARY
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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@ -510,14 +537,23 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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val p_rep = io.tiles(j).probe_rep
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val p_rep_data = io.tiles(j).probe_rep_data
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val idx = p_rep.bits.global_xact_id
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p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
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val pop_p_reps = trackerList.map(_.io.pop_p_rep(j).toBool)
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val do_pop = foldR(pop_p_reps)(_ || _)
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p_rep.ready := do_pop
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p_rep_data_dep_list(j).io.enq.valid := do_pop
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p_rep_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_p_reps)
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
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p_data_valid_arr(idx) := p_rep.valid && probeReplyHasData(p_rep.bits)
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p_data_tile_id_arr(idx) := UFix(j)
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p_rep_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_p_rep_dep(j).toBool))(_||_)
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}
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for( i <- 0 until NGLOBAL_XACTS ) {
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trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.valid
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trackerList(i).io.p_rep_data.bits := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.bits
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trackerList(i).io.p_rep_data_dep.valid := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.valid, (0 until NTILES).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.valid))
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trackerList(i).io.p_rep_data_dep.bits := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.bits))
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for( j <- 0 until NTILES) {
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val p_rep = io.tiles(j).probe_rep
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p_rep_cnt_dec_arr(i)(j) := p_rep.valid && (p_rep.bits.global_xact_id === UFix(i))
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@ -532,14 +568,14 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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val x_init = io.tiles(j).xact_init
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val x_init_data = io.tiles(j).xact_init_data
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val x_abort = io.tiles(j).xact_abort
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val abort_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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val conflicts = Bits(width = NGLOBAL_XACTS)
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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conflicts(UFix(i), t.busy && x_init.valid && coherenceConflict(t.addr, x_init.bits.address))
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}
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x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
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val abort_cnt = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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want_to_abort_arr(j) := conflicts.orR || busy_arr.toBits.andR
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want_to_abort_arr(j) := conflicts.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits))
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x_abort.valid := Bool(false)
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switch(abort_state_arr(j)) {
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@ -585,6 +621,9 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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trackerList(i).io.x_init_data.bits := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.bits
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trackerList(i).io.x_init_data.valid := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.valid
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//TODO trackerList(i).io.x_init_data_dep <> x_init_data_dep_arr(trackerList(i).io.init_tile_id)
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trackerList(i).io.x_init_data_dep.bits <> MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
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trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.valid, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid))
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}
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for( j <- 0 until NTILES ) {
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val x_init = io.tiles(j).xact_init
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@ -592,8 +631,13 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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init_arb.io.in(j).valid := (abort_state_arr(j) === s_idle) && !want_to_abort_arr(j) && x_init.valid
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init_arb.io.in(j).bits.xact_init := x_init.bits
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init_arb.io.in(j).bits.tile_id := UFix(j)
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x_init.ready := (abort_state_arr(j) === s_abort_complete) || foldR(trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.tile_id === UFix(j)))(_||_)
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val pop_x_inits = trackerList.map(_.io.pop_x_init && init_arb.io.out.bits.tile_id === UFix(j))
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val do_pop = foldR(pop_x_inits)(_||_)
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x_init_data_dep_list(j).io.enq.valid := do_pop
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x_init_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_x_inits)
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x_init.ready := (abort_state_arr(j) === s_abort_complete) || do_pop
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x_init_data.ready := (abort_state_arr(j) === s_abort_drain) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.tile_id === UFix(j)))(_||_)
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x_init_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_x_init_dep(j).toBool))(_||_)
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}
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alloc_arb.io.out.ready := init_arb.io.out.valid
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@ -85,6 +85,11 @@ object OHToUFix
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val out = MuxCase( UFix(0), (0 until in.getWidth).map( i => (in(i).toBool, UFix(i))))
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out.toUFix
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}
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def apply(in: Seq[Bool]): UFix =
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{
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val out = MuxCase( UFix(0), in.zipWithIndex map {case (b,i) => (b, UFix(i))})
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out.toUFix
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}
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}
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object UFixToOH
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@ -173,7 +178,7 @@ class ioDecoupled[+T <: Data]()(data: => T) extends Bundle
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val bits = data.asOutput
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}
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class ioPipe[T <: Data]()(data: => T) extends Bundle
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class ioPipe[+T <: Data]()(data: => T) extends Bundle
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{
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val valid = Bool(OUTPUT)
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val bits = data.asOutput
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