Henry Cook
35532420a8
Merge pull request #6 from ccelio/master
...
Clarified ptw/tlb/sret/cache I/O bundles
2015-03-03 18:01:26 -08:00
Christopher Celio
06dea3790a
Removed sret from ptw; sret now comes thru io.cpu to dcache
2015-03-03 16:50:41 -08:00
Christopher Celio
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
Henry Cook
1bed6ea498
New metadata-based coherence API
2015-02-28 17:32:03 -08:00
Henry Cook
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
Yunsup Lee
4f57985198
change organization to riscv
2015-02-17 14:43:11 -08:00
Henry Cook
0a8722e881
bugfix for indexing DataArray of of small L2
2015-02-17 00:37:40 -08:00
Henry Cook
0b131173e6
WritebackUnit multibeat control logic bugfix
2015-02-16 10:59:57 -08:00
Henry Cook
0c66e70f14
cleanup of conflicts; allocation bugfix
2015-02-06 13:20:44 -08:00
Albert Magyar
09cd555f29
Update riscv-tools pointer to prepare for HPCA workshop.
2015-02-04 13:29:04 -08:00
Henry Cook
7b86ea17cf
rename L2HellaCache to L2HellaCacheBank
2015-02-03 19:38:01 -08:00
Henry Cook
aa46b8b72d
Slightly refactor TLBResp
2015-02-03 19:32:37 -08:00
Stephen Twigg
3b3250339a
Explicitely convert results of Bits Muxes to UInt
...
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:15:01 -08:00
Stephen Twigg
3d35ccd401
Explicitely convert results of Bits Muxes to UInt
...
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
Henry Cook
57340be72b
doc update
2015-02-02 01:11:13 -08:00
Henry Cook
6141b3efc5
uncached -> builtin_type
2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f
Offset AMOs within beat and return old value
2015-02-02 00:22:21 -08:00
Henry Cook
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
Henry Cook
3aa030f960
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137
Block L2 transactions on the same set from proceeding in parallel
2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128
state machine bug on uncached write hits
2015-02-01 20:29:23 -08:00
Scott Beamer
00e074cdd9
fixes slight bug for non-power of 2 number of ras entries
2015-01-29 15:29:25 -08:00
Henry Cook
f58f8bf385
Make L2 data array use a single Mem
2015-01-25 15:37:04 -08:00
Scott Beamer
2a5dd907f5
bump chisel version
2015-01-06 16:59:10 -08:00
Andrew Waterman
a98127c09e
Merge branch 'ss-frontend'
2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3
Merge branch 'master' into ss-frontend
...
Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703
More control cleanup
2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11
Flush pipeline from MEM stage
...
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1
Continue refactoring control
2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9
Much refactor, so control
2015-01-03 13:34:38 -08:00
Henry Cook
1cb65d5ec1
%s/master/manager/g
2014-12-29 22:56:18 -08:00
Henry Cook
9ef00d187f
%s/master/manager/g + better comments
2014-12-29 22:55:58 -08:00
Henry Cook
c76b4bc21d
TileLink doc
2014-12-29 22:55:18 -08:00
Henry Cook
e62c71203e
disconnect unused outer network headers
2014-12-22 18:50:37 -08:00
Henry Cook
2ef4357ca8
acquire allocation bugfix
2014-12-19 17:39:23 -08:00
Henry Cook
f234fe65ce
Initial verison of L2WritebackUnit, passes MiT2 bmark tests
2014-12-19 03:03:53 -08:00
Henry Cook
d121af7f94
Simplify release handling
2014-12-18 17:12:29 -08:00
Henry Cook
77e5e6b561
refill bug
2014-12-17 19:29:28 -08:00
Henry Cook
bfcfc3fe18
refactor cache params
2014-12-17 14:28:14 -08:00
Henry Cook
08dcf4c6ca
refactor cache params
2014-12-17 14:28:05 -08:00
Henry Cook
ab39cbb15d
cleanup DirectoryRepresentation and coherence params
2014-12-15 19:24:42 -08:00
Henry Cook
d29793d1f7
cleanup CoherenceMetadata and coherence params
2014-12-15 19:23:38 -08:00
Andrew Waterman
d04da83f96
Make data RAMs 1RW instead of 1R1W
2014-12-15 17:36:17 -08:00
Henry Cook
6a8b66231c
Add uncached->cached tilelink converter
2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f
1R/W L2 data array?
...
Add TLDataBeats to new LLC; all bmarks pass
2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c
Finish adding TLDataBeats to uncore & hub
2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db
Begin adding TLDataBeats to uncore
2014-12-12 17:04:31 -08:00
Henry Cook
c9320862ae
add l2 dmem signal to rocc
2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b
multibeat TL; passes all tests
2014-12-12 16:54:33 -08:00
Henry Cook
404773eb9f
fix wb bug
2014-12-03 14:22:39 -08:00
