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riscv/rocket-chip
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3aa030f9605e0dbd87be440cd747e98d0320470b
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Henry Cook 3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
uncore
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
S
Description
Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
13 MiB
Languages
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
Verilog 0.8%
Other 0.7%
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