riscv/rocket-chip
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a999c055edb9b4d8ce1566401ec29716f1cc5ed2
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Author SHA1 Message Date
Andrew Waterman
a999c055ed Don't take an interrupt when EX stage PC is invalid 
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch.  EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.

h/t Yunsup
 2014-09-11 01:46:52 -07:00
Henry Cook
5eb5e9eaf5 Standardize ()=>Module(...) top-level Parameters 2014-09-07 17:54:41 -07:00
Henry Cook
5e2f98747f Merge branch 'dse' 2014-09-06 06:10:15 -07:00
Scott Beamer
600c5d50a9 better fix with explanation of sbt issue 2014-09-02 15:14:56 -07:00
Scott Beamer
f9922a106b fixes sbt error during first run 2014-09-02 14:34:36 -07:00
Henry Cook
b42a2ab40a Final parameter refactor 2014-09-01 13:28:58 -07:00
Adam Izraelevitz
2d6aafc32e Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD 2014-09-01 11:23:50 -07:00
Sagar Karandikar
83c6c2c9e2 rename refs to zynq-fpga to fpga-zynq 2014-08-29 10:26:48 -07:00
Henry Cook
6a4193cf90 minor cache param cleanup 2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26 a few more fixes. some param lookups fail (here() in Alter blocks) 2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Adam Izraelevitz
4e6d69892d Added initial brainstorm for parameter hierarchical flattening, does not compile ;) 2014-08-19 11:37:50 -07:00
Adam Izraelevitz
812353bace Ported FPU parameters to new Chisel Parameters 2014-08-19 11:37:27 -07:00
Yunsup Lee
4ac8e59b1f add .gitignore 2014-08-18 19:27:50 -07:00
Yunsup Lee
d520846638 add README and sbt files 2014-08-18 19:23:10 -07:00
Andrew Waterman
7bffc6c586 rename Unsigned.size to Unsigned.clog2 2014-06-14 13:58:07 -07:00
Andrew Waterman
3828c628c3 Remove vestigial control signals 2014-06-14 13:58:07 -07:00
Andrew Waterman
04593d433e clean up Int <-> Boolean conversion stuff 2014-06-14 13:58:07 -07:00
Andrew Waterman
ac88ded35a Use ROMs to reduce node count and improve QoR a bit 2014-06-14 13:58:07 -07:00
Andrew Waterman
88899eafe0 Reduce node count a bit 2014-06-14 13:58:07 -07:00
Jim Lawson
0c93567dea Replace needWidth() with getWidth. 2014-06-13 14:58:52 -07:00
Jim Lawson
de32595fba Quick change to work with new Width class. 2014-06-13 12:00:50 -07:00
Henry Cook
dab675b231 refactor Metadata, clean and expand coherence API 2014-05-28 16:05:48 -07:00
Andrew Waterman
8bc1c33540 Fix BTB error (requires Chisel update) 2014-05-19 18:56:30 -07:00
Andrew Waterman
cbb37ccc3e Use Mem instead of Vec[Reg] 2014-05-18 19:25:43 -07:00
Andrew Waterman
e91e12ed88 Fix RoCC accumulator example 2014-05-14 16:17:39 -07:00
Andrew Waterman
4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Andrew Waterman
94c1f01ec6 Deanonymize CSRFile's IO bundle 2014-05-09 19:30:57 -07:00
Andrew Waterman
fd5f419eb1 use getWidth instead of width 2014-05-09 19:30:57 -07:00
Andrew Waterman
0c13c00d08 Reduce node count by avoiding elsewhen :-( 2014-05-09 19:30:57 -07:00
Andrew Waterman
8dcc0cbb53 Fix bug with multiple DecodeLogics per module 2014-05-09 19:30:57 -07:00
Henry Cook
5bc6981414 fix metadata default, add bug TODO 2014-05-06 18:36:22 -07:00
Henry Cook
7d6a642c0c correct use of function value to initialize MetaDataArray 2014-05-06 13:00:00 -07:00
Henry Cook
7f690dd9c8 parameterize metadataarray 2014-05-01 01:45:45 -07:00
Henry Cook
519b2ea2b6 New metadata result trait 2014-04-26 19:08:56 -07:00
Henry Cook
1b156c6db9 TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:18:21 -07:00
Henry Cook
fc825c7103 MetaData & friends moved to uncore/ 2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7 Prep in HellaCache for extracting MetaData to uncore 2014-04-23 15:43:31 -07:00
Henry Cook
5c62cff2ce put replacement policy in uncore and minor nbdcache cleanups 2014-04-22 16:53:20 -07:00
Andrew Waterman
09e2ec1f9e Fix sign of remainder when dividing by zero 
h/t chris
 2014-04-18 16:32:57 -07:00
Henry Cook
1fa505f9ff remove superfluous AVec object 2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd Remove D$ -> BTB path 2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7 Fix critical path through integer scoreboard 2014-04-15 21:28:13 -07:00
Henry Cook
444d0449e3 io.cnt bug in serializer 2014-04-14 17:13:13 -07:00
Henry Cook
1da8ef2ddf Added serdes to decouple cache row size from tilelink data size 2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692 merge Aqcuire and AcquireData. cache line size coupled to tilelink data size 2014-04-10 12:09:52 -07:00
Stephen Twigg
e90f2484aa Sync with riscv-opcodes (csr register mapping) 2014-04-08 15:48:37 -07:00
Andrew Waterman
3ed8adf032 Add early out for MUL[W] (not MULH[[S]U]) 2014-04-07 23:48:02 -07:00