riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,489 Commits 1 Branch 0 Tags
a59fc3bdaa9bd208fbad18d662842efda29ae3a4
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Megan WachsandGitHub 338e453a91 JTAG: Use new withClock way of overriding clocks (#1072) 
* JTAG: Use new withClock way of overriding clocks

the override clock way is deprecated

* JTAG: use withClock instead of override clock

* JTAG:  extend Module for ClockedCounter

* JTAG: Don't use deprecated clock constructs

* JTAG: Remove another override_clock

* Rename "NegativeEdgeLatch"

because it's not a latch, it's just a register on the negative edge of the clock.

* Use the appropriately named NegEdgeReg

* JTAG: Rename another NegativeEdgeLatch
 2018-01-17 13:59:05 -08:00
Megan WachsandGitHub 6c6afc5bc9 Merge pull request #1191 from edcote/patch-2 
remove string type ambiguity in header
 2018-01-15 13:33:27 -08:00
Megan WachsandGitHub 8799508b1f Merge pull request #1179 from freechipsproject/refactored_rbb 
Add Debug tests to Regressions
 2018-01-12 10:34:48 -08:00
Megan Wachs 5fe0bb0d6a Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-09 21:34:14 -08:00
Megan Wachs a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-08 09:11:27 -08:00
Megan Wachs 427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs 2018-01-05 17:08:21 -08:00
Megan Wachs 76c5fd0c0c travis: Use newer infrastructure, but require sudo for additional disk space. 
This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
 2018-01-05 17:08:21 -08:00
Megan Wachs e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
Megan Wachs b643f3dca6 debug regressions: some whitespace and null ptr cleanup 2018-01-05 17:08:21 -08:00
Megan Wachs a97add954a Async Reg: Doesn't properly reset for Verilator. 2018-01-05 17:08:21 -08:00
Megan Wachs 9df3604007 emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
Megan Wachs 024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
Megan Wachs 1d3fa07c44 debug: print failures when debug tests fail, so we can see why it is failing on Travis 
Cleanups, and print out log names ASAP.

Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
 2018-01-05 17:08:15 -08:00
Megan Wachs 9b234216f0 debug: Install pexpect package for travis regressions 2018-01-05 16:13:19 -08:00
Megan Wachs 1549ecfb3f debug: explicitly clone riscv-tests to get to gdbserver.py 2018-01-05 16:13:11 -08:00
Megan Wachs 3de9a04272 debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN 2018-01-05 16:10:13 -08:00
Megan Wachs bd5fe5d22e Debug regression: have to say something about memory in order to run a simple test 2018-01-05 16:10:13 -08:00
Megan Wachs 5df55d7911 debug regression: bump riscv-tools for riscv-tests fixes 2018-01-05 16:10:13 -08:00
Megan Wachs 593839e0d5 Debug: add Debug regression to Travis regressions. 2018-01-05 16:10:00 -08:00
Megan Wachs 4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
 2018-01-05 16:02:52 -08:00
Megan WachsandGitHub 74d9326ebc JTAG: Revert to Chisel._ for Issue 1160 (#1161) 
* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
 2017-12-18 21:02:31 -08:00
Megan WachsandGitHub 9d489c6dcd Merge pull request #1128 from freechipsproject/chisel_527_fixed 
debug: Remove workaround for Chisel 3 #527
 2017-11-27 16:53:02 -08:00
Megan Wachs f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Megan WachsandGitHub 6229c7b1ff Merge pull request #1117 from freechipsproject/debug_test_tools 
debug: bump riscv-tools/riscv-tests/debug for Priv test fixes
 2017-11-17 20:54:41 -08:00
Megan Wachs 68c5981363 debug: bump riscv-tools/riscv-tests/debug for Priv test fixes 2017-11-17 16:06:50 -08:00
Megan WachsandGitHub e7704f46c8 Add some add'l debug features (#1112) 
* debug: Update macros from spec

* debug: some corrections in the auto-generated files

* debug: update renamed fields

* Debug: implement the implicit ebreak option for small program buffers

* debug: clean up some unused code and add more require() explanations

* debug: make implicit ebreak false

* debug: Add the havereset/haveresetack functionality

* debug: program buffer can still be 16 even if there is an implicit ebreak
 2017-11-16 17:14:41 -08:00
Megan WachsandGitHub 7e75d63ba6 debug: Bump riscv-tools for riscv-tests timeout fix (#1086) 
* debug: Bump riscv-tools for riscv-tests timeout fix

* bump riscv-tools now that is merged into master
 2017-11-02 14:05:02 -07:00
Megan WachsandGitHub f86489b59e JTAG: Use sorted map for stability (#1073) 
* JTAG: Use sorted map for stability

Otherwise the generated FIRRTL/Verilog is non deterministic

* jtag : parens for clarity

* jtag: Use deterministic ListMap and sort for stability

* JTAG: use slightly clearer SortedMap (clearer to me anyway)

* jtag: whitespace cleanup
 2017-10-31 15:33:41 -07:00
Megan WachsandGitHub 897b686377 Merge pull request #1066 from freechipsproject/diplomacy_paper 
Add link to Diplomatic Design Patterns Paper
 2017-10-23 16:52:01 -07:00
Megan WachsandGitHub ffffafc7c3 Add link to Diplomatic Design Patterns Paper 2017-10-23 15:21:46 -07:00
Megan WachsandGitHub e9e05b5f3b Add a check that MaxHartIdBits is enough for all hartids (#1054) 
* Add a check that MaxHartIdBits is enough for all hartids

* Correct off-by-one error in hartid check
 2017-10-13 15:20:35 -07:00
Megan Wachs 7b4c48d005 Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars 2017-10-11 15:10:50 -07:00
Megan WachsandGitHub 0e6aa7ae9d Merge pull request #1024 from freechipsproject/jtag_coverage 
Add Coverage points for JTAG TAP
 2017-10-09 12:29:18 -07:00
Megan Wachs 0916cf1bdd JTAG Coverage: Correct jtag_reset case 2017-10-09 09:54:15 -07:00
Megan Wachs 9efe1c448e Merge remote-tracking branch 'origin/master' into HEAD 2017-10-09 09:48:38 -07:00
Megan Wachs 9c9cb68462 JTAG Coverage: Add reset coverage points 2017-10-02 11:08:13 -07:00
Megan Wachs a8ab06d572 JTAG: Add coverage points to the JTAG Tap 2017-10-02 11:08:13 -07:00
Megan WachsandGitHub ffa3ab29ac Merge pull request #1006 from freechipsproject/async_reset_reg 
async_reset_reg: Don't randomize the register if rst is asserted anyway
 2017-09-21 11:48:04 -07:00
Megan Wachs cda89fbacb async_reset_reg: Don't randomize the register if rst is asserted anyway 2017-09-20 14:47:00 -07:00
Megan WachsandGitHub cbd65cd247 Merge pull request #992 from freechipsproject/test_mode_reset 
reset_catch: Allow Test Mode Overrides
 2017-09-18 14:16:49 -07:00
Megan Wachs 826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset 2017-09-18 09:50:27 -07:00
Megan Wachs c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset 2017-09-17 13:51:46 -07:00
Megan Wachs 215e072e5c test_mode_reset: fix typos 2017-09-17 13:51:40 -07:00
Megan Wachs 641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness 2017-09-15 16:36:35 -07:00
Megan Wachs 6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals 2017-09-15 12:30:39 -07:00
Megan Wachs ffc514d1bc test_mode_reset: Add missing file 2017-09-14 13:17:37 -07:00
Megan Wachs a0396b63e8 test_mode_reset: fix one bulk-connect gender issue 2017-09-14 13:16:13 -07:00
Megan Wachs 44edc5fdc3 test_mode_reset: Use simpler apply() method 2017-09-14 13:16:13 -07:00
Megan Wachs 82c00cb656 reset_catch: Allow Test Mode Overrides 2017-09-14 13:16:13 -07:00
Megan WachsandGitHub 929a924779 Merge pull request #975 from freechipsproject/async_reg 
Cleanup some register primitives
 2017-09-07 13:32:54 -07:00
Megan Wachs 1320f65ae6 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-07 11:27:36 -07:00
Megan WachsandGitHub b7acb6ca3d Merge pull request #986 from freechipsproject/jtag_vpi_reset 
jtag_vpi: add some hysteresis for waiting for init_done
 2017-09-07 11:26:42 -07:00
Megan Wachs 126d56b254 synchronizers: I learn how foldRight works 2017-09-07 10:48:27 -07:00
Megan Wachs 1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. 2017-09-07 09:57:50 -07:00
Megan WachsandGitHub f68390e458 jtag_vpi: Use a parameter for INIT_DELAY vs constant 2017-09-07 09:06:07 -07:00
Megan Wachs 19eabb6728 jtag_vpi: add some hysterisis for waiting for init_done 2017-09-06 18:13:04 -07:00
Megan Wachs dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg 2017-09-06 11:07:19 -07:00
Megan Wachs 3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary 2017-09-06 10:37:59 -07:00
Megan Wachs 777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place 2017-09-05 17:32:53 -07:00
Megan Wachs e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. 2017-09-05 15:54:25 -07:00
Megan Wachs 5df23c5514 Synchronizers: remove some newlines and unncessary gen's 2017-09-05 15:17:21 -07:00
Megan WachsandWesley W. Terpstra 667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming 2017-09-05 15:03:38 -07:00
Megan WachsandWesley W. Terpstra 94f06dc85c pbus: turn down overkill buffering between PBus and SBus 2017-09-05 15:03:38 -07:00
Megan WachsandWesley W. Terpstra c353f68dc0 buses: name dummy buffers too 2017-09-05 15:03:38 -07:00
Megan Wachs 57d0360c35 frontbus: Name the connection. 2017-08-30 18:07:34 -07:00
Megan Wachs c99afe4c66 buses: Name all the things. 2017-08-30 17:31:42 -07:00
Megan Wachs 183fefb2b9 Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in 2017-08-30 15:27:56 -07:00
Megan Wachs a3bc5f2e33 synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive 2017-08-30 12:59:16 -07:00
Megan Wachs 8139014c9e syncrhonizers: Remove unused sync from superclass 2017-08-30 12:33:03 -07:00
Megan Wachs 9dd6c4c32d synchronizers: New chisel ways of cloning type and use simpler lambda function 2017-08-30 12:11:14 -07:00
Megan Wachs bd32f0c122 synchronizers: properly pass parameters up to the superclass 2017-08-30 11:58:25 -07:00
Megan Wachs 483e63da19 synchronizers: Correctly pass the width through 2017-08-30 11:50:25 -07:00
Megan WachsandGitHub 91c3fa2865 Merge pull request #979 from freechipsproject/buffer_params_debuginfo 
TLBuffer: Add a nodedebugstring
 2017-08-29 17:52:50 -07:00
Megan Wachs a62ce0afe6 TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer. 2017-08-29 10:36:46 -07:00
Megan Wachs c473538e36 Merge remote-tracking branch 'origin/master' into async_reg 2017-08-28 17:19:03 -07:00
Megan Wachs 451334ac73 Add 1-deep synchronizer register for output of AsyncQueue 2017-08-28 17:18:54 -07:00
Megan Wachs 85c39b2f97 syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI 2017-08-24 17:47:04 -07:00
Megan Wachs 4e773f4738 syncregs: Use synchronizer primivites for LevelSyncCrossing 2017-08-24 17:42:31 -07:00
Megan Wachs 130b24355f syncregs: Use synchronizer primitives for IntXing 2017-08-24 17:39:07 -07:00
Megan Wachs 8b462d1595 syncregs: Use common primitives for AsyncQueue grey code synchronizers 2017-08-24 17:34:07 -07:00
Megan Wachs 3461cb47cc syncregs: Make Reset catcher use the synchronizer primitive 2017-08-24 17:26:38 -07:00
Megan Wachs c78ee9f0e4 syncreg: Refactor common code 2017-08-24 17:18:04 -07:00
Megan Wachs d83a6dc6af syncregs: Add utilities for Synchronizing Shift Registers 2017-08-24 16:55:17 -07:00
Megan WachsandGitHub bdaae40035 Merge pull request #973 from freechipsproject/named_buffers 
systemBus: allowing naming the TLBuffers which get inserted
 2017-08-24 16:31:14 -07:00
Megan Wachs 7f683eeb24 async_regs: Make modules have predictable names 2017-08-24 15:33:53 -07:00
Megan Wachs 0f75ebee92 async_reg: Rename the file to match scalastyle 2017-08-24 15:31:29 -07:00
Megan Wachs 103b6bc6d3 systemBus: allowing naming the TLBuffers which get inserted 2017-08-24 14:49:12 -07:00
Megan WachsandGitHub 6e689f55ed Merge pull request #965 from freechipsproject/quash_x 
async_reset_reg: Squash X's the same as for synchronous reg
 2017-08-21 16:48:25 -07:00
Megan Wachs 81890e3a42 async_reg: Clean up some funky indentation 2017-08-21 16:06:36 -07:00
Megan Wachs 4f45379863 async_reset_reg: Squash X's the same as for reset reg 2017-08-21 14:33:19 -07:00
Megan WachsandGitHub 1db4b3be9a Merge pull request #957 from freechipsproject/param_jtag_vpi 
jtag_vpi: Use Parameterized Black Box
 2017-08-14 18:37:30 -07:00
Megan Wachs 8783d51c97 jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed 2017-08-14 17:25:47 -07:00
Megan WachsandGitHub 57a5965bf4 Merge pull request #954 from freechipsproject/max-core-cycles 
Add a +max-core-cycles PlusArg
 2017-08-13 16:45:59 -07:00
Megan Wachs 88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Megan WachsandGitHub 017ac130c1 Merge pull request #922 from freechipsproject/bigger_tl_xbar 
TLXbar: Allow more masters and slaves and issue a warning.
 2017-08-03 16:52:56 -07:00
Megan Wachs 50c85f1b62 TLXbar: Allow more masters and slaves and issue a warning. 2017-08-03 15:46:06 -07:00
Megan WachsandGitHub 3fc7100048 Merge pull request #917 from freechipsproject/fuzzer_order 
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
 2017-08-02 18:39:59 -07:00
Megan WachsandGitHub d9821a74ce Merge pull request #916 from freechipsproject/transfer_sizes_print 
diplomacy: Pretty Print for TransferSizes
 2017-08-02 16:56:36 -07:00
Megan Wachs 595415d207 TLFuzzer: Correct the number of ordered clients created 2017-08-02 15:48:21 -07:00