riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Merge pull request #954 from freechipsproject/max-core-cycles

Browse Source 
Add a +max-core-cycles PlusArg
This commit is contained in:
Megan Wachs 2017-08-13 16:45:59 -07:00 committed by GitHub
commit 57a5965bf4
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/rocket/RocketCore.scala
View File

@ -702,6 +702,13 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
wb_reg_cinst, wb_reg_cinst)
}
val max_core_cycles = PlusArg("max-core-cycles",
default = 0,
docstring = "Maximum Core Clock cycles simulation may run before timeout. Ignored if 0 (Default).")
when (max_core_cycles > UInt(0)) {
assert (csr.io.time < max_core_cycles, "Maximum Core Cycles reached.")
}
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))