cf363b1fe4
add TileLink interconnect generator
2016-03-31 14:12:55 -07:00
adb7eacf6e
Fix Chisel3 build for XLen=32
2016-03-30 22:48:51 -07:00
70664bbca0
Fix Chisel3 build for UseVM=false
2016-03-30 22:48:31 -07:00
ab540d536a
bump uncore for split metadata chisel3 fix
2016-03-30 22:11:45 -07:00
d78066db5c
chisel3 fix for split metadata
2016-03-30 22:11:19 -07:00
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
be612e3843
bump rocket and uncore
2016-03-30 19:23:19 -07:00
3d990bdbef
workaround for Chisel3 name-aliasing issue
2016-03-30 19:15:22 -07:00
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
...
This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
e77900f540
Revert "switch back to Chisel2 for verilog build for now"
...
This reverts commit 3673365b08
2016-03-30 19:00:38 -07:00
8e601f26e1
switch back to the correct chisel3 and firrtl branches
2016-03-30 18:59:33 -07:00
8ad8e8a691
Add partial Sv48/Sv57 support
...
Right now, we don't support Sv39 and Sv48 at the same time, which needs
to change.
2016-03-30 11:02:22 -07:00
1e03408323
get rid of mt benchmark suite
2016-03-29 20:16:07 -07:00
cf716fea58
fix mm_dramsim2
2016-03-29 20:16:07 -07:00
3673365b08
switch back to Chisel2 for verilog build for now
2016-03-29 20:16:07 -07:00
265a82427e
add DefaultL2Config and DualCoreConfig to travis
2016-03-29 20:16:07 -07:00
ad93e0226d
Changes to prepare for switch to TileLink interconnect
...
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.
* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
2016-03-29 20:16:07 -07:00
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
38649bd4c1
some edits to groundtest regression tests
2016-03-29 20:16:07 -07:00
9b9c662952
fix w_last wire
2016-03-29 20:16:07 -07:00
2b61f28356
don't test DMA controller for now
2016-03-29 20:16:07 -07:00
e1a03cc9ac
fix issue with partial writemasks
2016-03-29 20:16:07 -07:00
e652821962
Use correct kind of TileLink arbiter
...
It was "correct" before, but broke Chisel3 build.
2016-03-28 22:53:47 -07:00
015992bc9e
no longer need MIFMasterTagBits
2016-03-28 12:24:11 -07:00
8e7f18084b
switch RTC to use TileLink instead of AXI
2016-03-28 12:23:16 -07:00
34852e406d
fix bug in NastiRouter
2016-03-28 12:22:43 -07:00
5ce3527b88
Merge pull request #32 from ucb-bar/pr-btb-masking
...
separate btb response mask from the frontend mask
2016-03-26 18:15:14 -07:00
f526d380fd
separate btb response mask from the frontend mask
...
It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
2016-03-26 05:37:26 -07:00
ed280fb3de
Remove empty when statement (???)
2016-03-25 15:52:18 -07:00
1ae6d09751
Slightly ameliorate D$->I$ critical path via scoreboard
2016-03-25 15:29:32 -07:00
6c48dc3471
Use more sensible knob values for SmallConfig
2016-03-25 14:18:24 -07:00
cce89f5fbc
Bump rocket
2016-03-25 14:18:15 -07:00
a4685a073f
Don't instantiate PTW when UseVM=false
2016-03-25 14:17:25 -07:00
27b3cca046
Discover D$, PTW port counts dynamically
...
This is a generator, after all...
2016-03-25 14:16:56 -07:00
af3bc1cb79
don't use ROM for partial writemask regression
2016-03-25 14:06:06 -07:00
5372f181b1
add in missing connections for regression test
2016-03-25 14:05:52 -07:00
7f8f138d6a
fix addPendingBitWhenPartialWritemask
2016-03-24 20:01:50 -07:00
11bd15432a
fix bug in RTC
2016-03-24 20:01:50 -07:00
00b3908d92
git rid of reorder queue in narrower
2016-03-24 20:01:50 -07:00
8d1ba4d1ec
Remove hard-coded XLEN values from D$
2016-03-24 14:52:12 -07:00
d1639416cb
Merge pull request #77 from ucb-bar/chisel3
...
Preliminary Chisel 3 Support
2016-03-24 12:56:36 -07:00
39cf945efb
Use Chisel 3 to build verilog on Travis
...
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
cddfdf0929
Add CHISEL_VERSION make argument
...
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
d697559754
Correct the polarity of the non-backup-memory HTIF
...
This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
7d5eac189b
Bump the uncore for some Chisel3 fixes
2016-03-24 12:00:13 -07:00
4744deec28
Fix the SCR file for Chisel 3
2016-03-24 12:00:13 -07:00
476db6ef39
Move to a newer Scala version
...
Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
c6e974b110
Merge pull request #30 from ucb-bar/chisel3
...
Chisel 3 support
2016-03-24 11:52:02 -07:00
471f4c2695
change WriteMaskedPutBlockRegression for better bug detection
...
Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
2016-03-23 16:31:19 -07:00
c9e1b72972
Don't assign SInt(-1) to a UInt
2016-03-23 16:24:27 -07:00
