riscv/rocket-chip
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7f88a00a38
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57 Commits

Author SHA1 Message Date
Andrew Waterman
7f88a00a38 Always verify BTB result; don't bother flushing it 
This improves CPI for things like

    lbu t0, (t0)
    j foo
    addi t0, t0, 1

where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
 2016-06-23 00:01:06 -07:00
Andrew Waterman
60bddddfe6 Merge sptbr and sasid 2016-06-17 18:29:05 -07:00
Andrew Waterman
0b4c8e9af7 Add D-mode single-step support 2016-06-15 16:21:24 -07:00
Andrew Waterman
e3b4b55836 Refactor breakpoints and support range comparison (currently disabled) 2016-06-10 19:55:58 -07:00
Andrew Waterman
dca55a2b35 Respect breakpoint privilege settings 2016-06-09 12:41:52 -07:00
Andrew Waterman
c85ea7b987 Set badaddr on breakpoints 2016-06-09 12:33:43 -07:00
Andrew Waterman
e3c17b5f74 Add provisional breakpoint support 2016-06-08 20:19:52 -07:00
Andrew Waterman
9949347569 First stab at debug interrupts 2016-06-01 16:57:10 -07:00
Andrew Waterman
51379621d6 Flush blocking D$ on FENCE.I 2016-05-31 19:27:28 -07:00
Andrew Waterman
00ea9a7d82 Remove most of mstatus when user mode isn't supported 2016-05-25 15:37:32 -07:00
Andrew Waterman
9aa724706e Don't include RV64 instructions in RV32 decode table 2016-05-25 14:26:45 -07:00
Andrew Waterman
354cb2d5ec Don't stall I$ response when resolving a branch misprediction 
This avoids a fetch bubble.

Not clear if this is the best way to do it.  Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
 2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e Support disabling atomics extension 2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4 Stall on D$ lockups less conservatively 2016-05-24 15:05:41 -07:00
Andrew Waterman
4aef567a80 Fix MMIO bug: replay_next wasn't set 2016-05-13 17:59:53 -07:00
Andrew Waterman
742c05d6a7 Pipeline D$->I$ control paths 
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
 2016-05-13 17:07:28 -07:00
Colin Schmidt
8fa2de0816 chisel3 fix to RoCC connections honor last connect 2016-05-05 18:09:48 -07:00
Andrew Waterman
f784f4da93 Rename PRCICoreIO to PRCITileIO 2016-05-02 18:08:01 -07:00
Andrew Waterman
83fa489cef Stop using HTIF CSR port 
The port itself is still present to keep other stuff compiling.
 2016-05-02 14:40:52 -07:00
Andrew Waterman
84fd45fd77 Pass TLB flush signal to I$ explicitly 2016-04-22 15:20:17 -07:00
Howard Mao
b7527268bb use address map instead of MMIOBase to find size of memory 2016-04-21 18:44:39 -07:00
Andrew Waterman
51e0870e23 Separate I$ and D$ interface signals that span clock cycles 
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
 2016-04-01 19:30:39 -07:00
Andrew Waterman
37b9051762 No need to validate npc if BTB is disabled 2016-04-01 15:54:57 -07:00
Andrew Waterman
7ae44d4905 Add RV32 support 2016-03-10 17:32:00 -08:00
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3 make mtvec configurable and writeable 2016-01-29 14:51:56 -08:00
Howard Mao
305185c034 send DMA requests through MMIO and get responses through CSRs 2016-01-29 14:51:56 -08:00
Howard Mao
d51c127646 fix deprecation warnings in rocket.scala 2016-01-13 22:08:06 -08:00
Howard Mao
e80340198a use implicit parameters for ALU 2015-11-30 17:35:33 -08:00
Andrew Waterman
e203b8b378 Make ALU generic for zscale 2015-11-24 19:17:07 -08:00
Andrew Waterman
5294e94794 Remove CSR back pressure ability 
We were using it for IPIs, but no longer need it.
 2015-11-24 18:28:14 -08:00
Andrew Waterman
4616db4695 Make RegFile/ImmGen usable by zscale 2015-11-24 18:27:07 -08:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Henry Cook
1a1185be3f Vectorize ROCC and Tile memory interfaces 2015-10-20 15:02:24 -07:00
Henry Cook
8173695800 added HasAddrMapParameters 2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Howard Mao
9eb988a4c6 make sure access to invalid physical address treated as exception 2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a don't mux data_word_bypass between IOMSHR and cache 2015-09-22 10:10:57 -07:00
Christopher Celio
76bf1da310 [commitlog] zero-extend SP write-back values 2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c [commitlog] don't print out writebacks to x0 2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262 [commitlog] Added privilege-level to output 2015-09-15 16:47:24 -07:00
Christopher Celio
d630a03857 [commitlog] Added FP instructions to the commitlog 2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c [commitlog] Initial commit log for integer working 2015-09-15 15:59:03 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
ef319edc84 Bits -> UInt 2015-08-02 21:03:42 -07:00
Andrew Waterman
52fc34a138 Chisel3: bulk connect is not commutative 
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
 2015-08-01 21:11:25 -07:00
Andrew Waterman
6c0e1e33ab Purge UInt := SInt assignments 2015-07-31 15:42:10 -07:00