7f88a00a38
This improves CPI for things like
lbu t0, (t0)
j foo
addi t0, t0, 1
where the addi would stall, causing j's misprediction check to fail,
flushing the pipeline.
669 lines
28 KiB
Scala
669 lines
28 KiB
Scala
// See LICENSE for license details.
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package rocket
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import Chisel._
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import junctions._
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import uncore._
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import Util._
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import cde.{Parameters, Field}
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case object UseFPU extends Field[Boolean]
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case object FDivSqrt extends Field[Boolean]
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case object XLen extends Field[Int]
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case object FetchWidth extends Field[Int]
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case object RetireWidth extends Field[Int]
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case object UseVM extends Field[Boolean]
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case object UseUser extends Field[Boolean]
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case object UseDebug extends Field[Boolean]
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case object UseAtomics extends Field[Boolean]
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case object UsePerfCounters extends Field[Boolean]
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case object FastLoadWord extends Field[Boolean]
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case object FastLoadByte extends Field[Boolean]
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case object FastMulDiv extends Field[Boolean]
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case object CoreInstBits extends Field[Int]
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case object CoreDataBits extends Field[Int]
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case object CoreDCacheReqTagBits extends Field[Int]
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case object NCustomMRWCSRs extends Field[Int]
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case object MtvecWritable extends Field[Boolean]
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case object MtvecInit extends Field[BigInt]
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case object ResetVector extends Field[BigInt]
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case object NBreakpoints extends Field[Int]
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trait HasCoreParameters extends HasAddrMapParameters {
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implicit val p: Parameters
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val xLen = p(XLen)
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val usingVM = p(UseVM)
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val usingUser = p(UseUser)
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val usingDebug = p(UseDebug)
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val usingFPU = p(UseFPU)
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val usingAtomics = p(UseAtomics)
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val usingFDivSqrt = p(FDivSqrt)
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val usingRoCC = !p(BuildRoCC).isEmpty
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val usingFastMulDiv = p(FastMulDiv)
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val fastLoadWord = p(FastLoadWord)
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val fastLoadByte = p(FastLoadByte)
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val retireWidth = p(RetireWidth)
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val fetchWidth = p(FetchWidth)
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val coreInstBits = p(CoreInstBits)
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val coreInstBytes = coreInstBits/8
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val coreDataBits = xLen
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val coreDataBytes = coreDataBits/8
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val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1))
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val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
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val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
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val coreMaxAddrBits = paddrBits max vaddrBitsExtended
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val nCustomMrwCsrs = p(NCustomMRWCSRs)
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val roccCsrs = if (p(BuildRoCC).isEmpty) Nil
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else p(BuildRoCC).flatMap(_.csrs)
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val nRoccCsrs = p(RoccNCSRs)
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val nCores = p(HtifKey).nCores
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// Print out log of committed instructions and their writeback values.
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// Requires post-processing due to out-of-order writebacks.
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val enableCommitLog = false
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val usingPerfCounters = p(UsePerfCounters)
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val maxPAddrBits = xLen match {
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case 32 => 34
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case 64 => 50
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}
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require(paddrBits < maxPAddrBits)
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require(!fastLoadByte || fastLoadWord)
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}
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abstract class CoreModule(implicit val p: Parameters) extends Module
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with HasCoreParameters
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abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasCoreParameters
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class RegFile(n: Int, w: Int, zero: Boolean = false) {
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private val rf = Mem(n, UInt(width = w))
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private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
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private val reads = collection.mutable.ArrayBuffer[(UInt,UInt)]()
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private var canRead = true
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def read(addr: UInt) = {
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require(canRead)
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reads += addr -> Wire(UInt())
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reads.last._2 := Mux(Bool(zero) && addr === UInt(0), UInt(0), access(addr))
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reads.last._2
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}
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def write(addr: UInt, data: UInt) = {
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canRead = false
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when (addr =/= UInt(0)) {
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access(addr) := data
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for ((raddr, rdata) <- reads)
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when (addr === raddr) { rdata := data }
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}
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}
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}
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object ImmGen {
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def apply(sel: UInt, inst: UInt) = {
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val sign = Mux(sel === IMM_Z, SInt(0), inst(31).toSInt)
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val b30_20 = Mux(sel === IMM_U, inst(30,20).toSInt, sign)
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val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).toSInt)
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val b11 = Mux(sel === IMM_U || sel === IMM_Z, SInt(0),
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Mux(sel === IMM_UJ, inst(20).toSInt,
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Mux(sel === IMM_SB, inst(7).toSInt, sign)))
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val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, Bits(0), inst(30,25))
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val b4_1 = Mux(sel === IMM_U, Bits(0),
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Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
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Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
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val b0 = Mux(sel === IMM_S, inst(7),
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Mux(sel === IMM_I, inst(20),
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Mux(sel === IMM_Z, inst(15), Bits(0))))
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Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).toSInt
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}
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}
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class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val prci = new PRCITileIO().flip
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val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
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val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
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val ptw = new DatapathPTWIO().flip
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val fpu = new FPUIO().flip
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val rocc = new RoCCInterface().flip
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}
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val decode_table = {
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(if (true) new MDecode +: (if (xLen > 32) Seq(new M64Decode) else Nil) else Nil) ++:
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(if (usingAtomics) new ADecode +: (if (xLen > 32) Seq(new A64Decode) else Nil) else Nil) ++:
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(if (usingFPU) new FDecode +: (if (xLen > 32) Seq(new F64Decode) else Nil) else Nil) ++:
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(if (usingFPU && usingFDivSqrt) Some(new FDivSqrtDecode) else None) ++:
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(if (usingRoCC) Some(new RoCCDecode) else None) ++:
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(if (xLen > 32) Some(new I64Decode) else None) ++:
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(if (usingVM) Some(new SDecode) else None) ++:
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(if (usingDebug) Some(new DebugDecode) else None) ++:
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Seq(new IDecode)
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} flatMap(_.table)
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val ex_ctrl = Reg(new IntCtrlSigs)
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val mem_ctrl = Reg(new IntCtrlSigs)
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val wb_ctrl = Reg(new IntCtrlSigs)
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val ex_reg_xcpt_interrupt = Reg(Bool())
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val ex_reg_valid = Reg(Bool())
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val ex_reg_btb_hit = Reg(Bool())
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val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val ex_reg_xcpt = Reg(Bool())
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val ex_reg_flush_pipe = Reg(Bool())
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val ex_reg_load_use = Reg(Bool())
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val ex_reg_cause = Reg(UInt())
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val mem_reg_xcpt_interrupt = Reg(Bool())
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val mem_reg_valid = Reg(Bool())
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val mem_reg_btb_hit = Reg(Bool())
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val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits)
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val mem_reg_xcpt = Reg(Bool())
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val mem_reg_replay = Reg(Bool())
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val mem_reg_flush_pipe = Reg(Bool())
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val mem_reg_cause = Reg(UInt())
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val mem_reg_slow_bypass = Reg(Bool())
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val mem_reg_load = Reg(Bool())
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val mem_reg_store = Reg(Bool())
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val mem_reg_pc = Reg(UInt())
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val mem_reg_inst = Reg(Bits())
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val mem_reg_wdata = Reg(Bits())
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val mem_reg_rs2 = Reg(Bits())
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val take_pc_mem = Wire(Bool())
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val wb_reg_valid = Reg(Bool())
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val wb_reg_xcpt = Reg(Bool())
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val wb_reg_mem_xcpt = Reg(Bool())
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val wb_reg_replay = Reg(Bool())
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val wb_reg_cause = Reg(UInt())
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val wb_reg_rocc_pending = Reg(init=Bool(false))
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val wb_reg_pc = Reg(UInt())
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val wb_reg_inst = Reg(Bits())
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val wb_reg_wdata = Reg(Bits())
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val wb_reg_rs2 = Reg(Bits())
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val take_pc_wb = Wire(Bool())
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val take_pc_mem_wb = take_pc_wb || take_pc_mem
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val take_pc = take_pc_mem_wb
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// decode stage
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val id_pc = io.imem.resp.bits.pc
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val id_inst = io.imem.resp.bits.data(0).toBits; require(fetchWidth == 1)
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val id_ctrl = Wire(new IntCtrlSigs()).decode(id_inst, decode_table)
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val id_raddr3 = id_inst(31,27)
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val id_raddr2 = id_inst(24,20)
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val id_raddr1 = id_inst(19,15)
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val id_waddr = id_inst(11,7)
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val id_load_use = Wire(Bool())
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val id_reg_fence = Reg(init=Bool(false))
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val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
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val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
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val rf = new RegFile(31, xLen)
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val id_rs = id_raddr.map(rf.read _)
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val ctrl_killd = Wire(Bool())
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val csr = Module(new CSRFile)
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val id_csr_en = id_ctrl.csr =/= CSR.N
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val id_system_insn = id_ctrl.csr === CSR.I
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val id_csr_ren = (id_ctrl.csr === CSR.S || id_ctrl.csr === CSR.C) && id_raddr1 === UInt(0)
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val id_csr = Mux(id_csr_ren, CSR.R, id_ctrl.csr)
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val id_csr_addr = id_inst(31,20)
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// this is overly conservative
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val safe_csrs = CSRs.sscratch :: CSRs.sepc :: CSRs.mscratch :: CSRs.mepc :: CSRs.mcause :: CSRs.mbadaddr :: Nil
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val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
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val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && !DecodeLogic(id_csr_addr, safe_csrs.map(UInt(_)), (legal_csrs -- safe_csrs).toList.map(UInt(_))))
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val id_illegal_insn = !id_ctrl.legal ||
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id_ctrl.fp && !csr.io.status.fs.orR ||
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id_ctrl.rocc && !csr.io.status.xs.orR
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// stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE)
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val id_amo_aq = id_inst(26)
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val id_amo_rl = id_inst(25)
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val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl
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val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
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val id_rocc_busy = Bool(usingRoCC) &&
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(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
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mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
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id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy
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val id_do_fence = id_rocc_busy && id_ctrl.fence ||
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id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_en)
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val bpu = Module(new BreakpointUnit)
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bpu.io.status := csr.io.status
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bpu.io.bp := csr.io.bp
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bpu.io.pc := id_pc
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bpu.io.ea := mem_reg_wdata
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val (id_xcpt, id_cause) = checkExceptions(List(
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(csr.io.interrupt, csr.io.interrupt_cause),
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(bpu.io.xcpt_if, UInt(Causes.breakpoint)),
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(io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)),
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(id_illegal_insn, UInt(Causes.illegal_instruction))))
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val dcache_bypass_data =
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if (fastLoadByte) io.dmem.resp.bits.data
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
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else wb_reg_wdata
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// detect bypass opportunities
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val ex_waddr = ex_reg_inst(11,7)
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val mem_waddr = mem_reg_inst(11,7)
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val wb_waddr = wb_reg_inst(11,7)
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val bypass_sources = IndexedSeq(
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(Bool(true), UInt(0), UInt(0)), // treat reading x0 as a bypass
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(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
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(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
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(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
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val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
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// execute stage
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val bypass_mux = Vec(bypass_sources.map(_._3))
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val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
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val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt()))
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val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))
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val ex_rs = for (i <- 0 until id_raddr.size)
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yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
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val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
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val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, SInt(0), Seq(
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A1_RS1 -> ex_rs(0).toSInt,
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A1_PC -> ex_reg_pc.toSInt))
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val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, SInt(0), Seq(
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A2_RS2 -> ex_rs(1).toSInt,
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A2_IMM -> ex_imm,
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A2_FOUR -> SInt(4)))
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val alu = Module(new ALU)
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alu.io.dw := ex_ctrl.alu_dw
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alu.io.fn := ex_ctrl.alu_fn
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alu.io.in2 := ex_op2.toUInt
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alu.io.in1 := ex_op1.toUInt
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// multiplier and divider
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val div = Module(new MulDiv(width = xLen,
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unroll = if(usingFastMulDiv) 8 else 1,
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earlyOut = usingFastMulDiv))
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div.io.req.valid := ex_reg_valid && ex_ctrl.div
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div.io.req.bits.dw := ex_ctrl.alu_dw
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div.io.req.bits.fn := ex_ctrl.alu_fn
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div.io.req.bits.in1 := ex_rs(0)
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div.io.req.bits.in2 := ex_rs(1)
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div.io.req.bits.tag := ex_waddr
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ex_reg_valid := !ctrl_killd
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ex_reg_xcpt := !ctrl_killd && id_xcpt
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ex_reg_xcpt_interrupt := csr.io.interrupt && !take_pc && io.imem.resp.valid
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when (id_xcpt) { ex_reg_cause := id_cause }
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when (!ctrl_killd) {
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ex_ctrl := id_ctrl
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ex_ctrl.csr := id_csr
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ex_reg_btb_hit := io.imem.btb_resp.valid
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when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits }
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ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep
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ex_reg_load_use := id_load_use
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for (i <- 0 until id_raddr.size) {
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val do_bypass = id_bypass_src(i).reduce(_||_)
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val bypass_src = PriorityEncoder(id_bypass_src(i))
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ex_reg_rs_bypass(i) := do_bypass
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ex_reg_rs_lsb(i) := bypass_src
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when (id_ren(i) && !do_bypass) {
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ex_reg_rs_lsb(i) := id_rs(i)(bypass_src.getWidth-1,0)
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ex_reg_rs_msb(i) := id_rs(i) >> bypass_src.getWidth
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}
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}
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}
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when (!ctrl_killd || csr.io.interrupt) {
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ex_reg_inst := id_inst
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ex_reg_pc := id_pc
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}
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// replay inst in ex stage?
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val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid
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val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||
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ex_ctrl.div && !div.io.req.ready
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val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use
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val replay_ex = ex_reg_valid && (replay_ex_structural || replay_ex_load_use)
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val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid
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// detect 2-cycle load-use delay for LB/LH/SC
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val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || Vec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_ctrl.mem_type)
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val (ex_xcpt, ex_cause) = checkExceptions(List(
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(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
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(ex_ctrl.fp && io.fpu.illegal_rm, UInt(Causes.illegal_instruction))))
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// memory stage
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val mem_br_taken = mem_reg_wdata(0)
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val mem_br_target = mem_reg_pc.toSInt +
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Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
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Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_int_wdata = Mux(mem_ctrl.jalr, mem_br_target, mem_reg_wdata.toSInt).toUInt
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val mem_npc = (Mux(mem_ctrl.jalr, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).toSInt, mem_br_target) & SInt(-2)).toUInt
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val mem_wrong_npc = Mux(ex_reg_valid, mem_npc =/= ex_reg_pc, Mux(io.imem.resp.valid, mem_npc =/= id_pc, Bool(true)))
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val mem_npc_misaligned = mem_npc(1)
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val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
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val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
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val mem_misprediction =
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if (p(BtbKey).nEntries == 0) mem_cfi_taken
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else mem_wrong_npc
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val want_take_pc_mem = mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe)
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take_pc_mem := want_take_pc_mem && !mem_npc_misaligned
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mem_reg_valid := !ctrl_killx
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mem_reg_replay := !take_pc_mem_wb && replay_ex
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mem_reg_xcpt := !ctrl_killx && ex_xcpt
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mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt
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when (ex_xcpt) { mem_reg_cause := ex_cause }
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when (ex_reg_valid || ex_reg_xcpt_interrupt) {
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mem_ctrl := ex_ctrl
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mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
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mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
|
|
mem_reg_btb_hit := ex_reg_btb_hit
|
|
when (ex_reg_btb_hit) { mem_reg_btb_resp := ex_reg_btb_resp }
|
|
mem_reg_flush_pipe := ex_reg_flush_pipe
|
|
mem_reg_slow_bypass := ex_slow_bypass
|
|
|
|
mem_reg_inst := ex_reg_inst
|
|
mem_reg_pc := ex_reg_pc
|
|
mem_reg_wdata := alu.io.out
|
|
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc)) {
|
|
mem_reg_rs2 := ex_rs(1)
|
|
}
|
|
}
|
|
|
|
val (mem_new_xcpt, mem_new_cause) = checkExceptions(List(
|
|
(mem_reg_load && bpu.io.xcpt_ld, UInt(Causes.breakpoint)),
|
|
(mem_reg_store && bpu.io.xcpt_st, UInt(Causes.breakpoint)),
|
|
(want_take_pc_mem && mem_npc_misaligned, UInt(Causes.misaligned_fetch)),
|
|
(mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)),
|
|
(mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)),
|
|
(mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)),
|
|
(mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load))))
|
|
|
|
val (mem_xcpt, mem_cause) = checkExceptions(List(
|
|
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
|
|
(mem_reg_valid && mem_new_xcpt, mem_new_cause)))
|
|
|
|
val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
|
|
val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
|
|
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem
|
|
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
|
|
div.io.kill := killm_common && Reg(next = div.io.req.fire())
|
|
val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem
|
|
|
|
// writeback stage
|
|
wb_reg_valid := !ctrl_killm
|
|
wb_reg_replay := replay_mem && !take_pc_wb
|
|
wb_reg_xcpt := mem_xcpt && !take_pc_wb
|
|
wb_reg_mem_xcpt := mem_reg_valid && mem_new_xcpt && !(mem_reg_xcpt_interrupt || mem_reg_xcpt)
|
|
when (mem_xcpt) { wb_reg_cause := mem_cause }
|
|
when (mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt) {
|
|
wb_ctrl := mem_ctrl
|
|
wb_reg_wdata := Mux(mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
|
|
when (mem_ctrl.rocc) {
|
|
wb_reg_rs2 := mem_reg_rs2
|
|
}
|
|
wb_reg_inst := mem_reg_inst
|
|
wb_reg_pc := mem_reg_pc
|
|
}
|
|
|
|
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc
|
|
val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
|
|
val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
|
|
val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
|
|
val wb_xcpt = wb_reg_xcpt || csr.io.csr_xcpt
|
|
take_pc_wb := replay_wb || wb_xcpt || csr.io.eret
|
|
|
|
when (wb_rocc_val) { wb_reg_rocc_pending := !io.rocc.cmd.ready }
|
|
when (wb_reg_xcpt) { wb_reg_rocc_pending := Bool(false) }
|
|
|
|
// writeback arbitration
|
|
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
|
|
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
|
|
val dmem_resp_waddr = io.dmem.resp.bits.tag >> 1
|
|
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
|
|
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
|
|
|
|
div.io.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
|
|
val ll_wdata = Wire(init = div.io.resp.bits.data)
|
|
val ll_waddr = Wire(init = div.io.resp.bits.tag)
|
|
val ll_wen = Wire(init = div.io.resp.fire())
|
|
if (usingRoCC) {
|
|
io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
|
|
when (io.rocc.resp.fire()) {
|
|
div.io.resp.ready := Bool(false)
|
|
ll_wdata := io.rocc.resp.bits.data
|
|
ll_waddr := io.rocc.resp.bits.rd
|
|
ll_wen := Bool(true)
|
|
}
|
|
}
|
|
when (dmem_resp_replay && dmem_resp_xpu) {
|
|
div.io.resp.ready := Bool(false)
|
|
if (usingRoCC)
|
|
io.rocc.resp.ready := Bool(false)
|
|
ll_waddr := dmem_resp_waddr
|
|
ll_wen := Bool(true)
|
|
}
|
|
|
|
val wb_valid = wb_reg_valid && !replay_wb && !csr.io.csr_xcpt
|
|
val wb_wen = wb_valid && wb_ctrl.wxd
|
|
val rf_wen = wb_wen || ll_wen
|
|
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
|
|
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
|
|
Mux(ll_wen, ll_wdata,
|
|
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
|
|
wb_reg_wdata)))
|
|
when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
|
|
|
|
// hook up control/status regfile
|
|
csr.io.exception := wb_reg_xcpt
|
|
csr.io.cause := wb_reg_cause
|
|
csr.io.retire := wb_valid
|
|
csr.io.prci <> io.prci
|
|
io.fpu.fcsr_rm := csr.io.fcsr_rm
|
|
csr.io.fcsr_flags := io.fpu.fcsr_flags
|
|
io.rocc.csr <> csr.io.rocc.csr
|
|
csr.io.rocc.interrupt <> io.rocc.interrupt
|
|
csr.io.pc := wb_reg_pc
|
|
csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
|
|
csr.io.uarch_counters.foreach(_ := Bool(false))
|
|
io.ptw.ptbr := csr.io.ptbr
|
|
io.ptw.invalidate := csr.io.fatc
|
|
io.ptw.status := csr.io.status
|
|
csr.io.rw.addr := wb_reg_inst(31,20)
|
|
csr.io.rw.cmd := Mux(wb_reg_valid, wb_ctrl.csr, CSR.N)
|
|
csr.io.rw.wdata := wb_reg_wdata
|
|
|
|
val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= UInt(0), id_raddr1),
|
|
(id_ctrl.rxs2 && id_raddr2 =/= UInt(0), id_raddr2),
|
|
(id_ctrl.wxd && id_waddr =/= UInt(0), id_waddr))
|
|
val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),
|
|
(io.fpu.dec.ren2, id_raddr2),
|
|
(io.fpu.dec.ren3, id_raddr3),
|
|
(io.fpu.dec.wen, id_waddr))
|
|
|
|
val sboard = new Scoreboard(32)
|
|
sboard.clear(ll_wen, ll_waddr)
|
|
val id_sboard_hazard = checkHazards(hazard_targets, sboard.read _)
|
|
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
|
|
|
|
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
|
|
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc
|
|
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
|
|
val fp_data_hazard_ex = ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
|
|
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
|
|
|
|
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
|
|
val mem_mem_cmd_bh =
|
|
if (fastLoadWord) Bool(!fastLoadByte) && mem_reg_slow_bypass
|
|
else Bool(true)
|
|
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc
|
|
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
|
|
val fp_data_hazard_mem = mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
|
|
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
|
|
id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem
|
|
|
|
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
|
|
val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)
|
|
val fp_data_hazard_wb = wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
|
|
val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
|
|
|
|
val id_stall_fpu = if (usingFPU) {
|
|
val fp_sboard = new Scoreboard(32)
|
|
fp_sboard.set((wb_dcache_miss && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
|
|
fp_sboard.clear(dmem_resp_replay && dmem_resp_fpu, dmem_resp_waddr)
|
|
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
|
|
|
|
id_csr_en && !io.fpu.fcsr_rdy || checkHazards(fp_hazard_targets, fp_sboard.read _)
|
|
} else Bool(false)
|
|
|
|
val dcache_blocked = Reg(Bool())
|
|
dcache_blocked := !io.dmem.req.ready && (io.dmem.req.valid || dcache_blocked)
|
|
|
|
val ctrl_stalld =
|
|
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
|
|
id_ctrl.fp && id_stall_fpu ||
|
|
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
|
|
Bool(usingRoCC) && wb_reg_rocc_pending && id_ctrl.rocc && !io.rocc.cmd.ready ||
|
|
id_do_fence ||
|
|
csr.io.csr_stall
|
|
ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || csr.io.interrupt
|
|
|
|
io.imem.req.valid := take_pc
|
|
io.imem.req.bits.pc :=
|
|
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
|
|
Mux(replay_wb, wb_reg_pc, // replay
|
|
mem_npc)).toUInt // mispredicted branch
|
|
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
|
|
io.imem.flush_tlb := csr.io.fatc
|
|
io.imem.resp.ready := !ctrl_stalld || csr.io.interrupt || take_pc_mem
|
|
|
|
io.imem.btb_update.valid := mem_reg_valid && !mem_npc_misaligned && mem_wrong_npc && mem_cfi_taken && !take_pc_wb
|
|
io.imem.btb_update.bits.isJump := mem_ctrl.jal || mem_ctrl.jalr
|
|
io.imem.btb_update.bits.isReturn := mem_ctrl.jalr && mem_reg_inst(19,15) === BitPat("b00??1")
|
|
io.imem.btb_update.bits.pc := mem_reg_pc
|
|
io.imem.btb_update.bits.target := io.imem.req.bits.pc
|
|
io.imem.btb_update.bits.br_pc := mem_reg_pc
|
|
io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
|
|
io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
|
|
|
|
io.imem.bht_update.valid := mem_reg_valid && mem_ctrl.branch && !take_pc_wb
|
|
io.imem.bht_update.bits.pc := mem_reg_pc
|
|
io.imem.bht_update.bits.taken := mem_br_taken
|
|
io.imem.bht_update.bits.mispredict := mem_wrong_npc
|
|
io.imem.bht_update.bits.prediction := io.imem.btb_update.bits.prediction
|
|
|
|
io.imem.ras_update.valid := mem_reg_valid && io.imem.btb_update.bits.isJump && !mem_npc_misaligned && !take_pc_wb
|
|
io.imem.ras_update.bits.returnAddr := mem_int_wdata
|
|
io.imem.ras_update.bits.isCall := mem_ctrl.wxd && mem_waddr(0)
|
|
io.imem.ras_update.bits.isReturn := io.imem.btb_update.bits.isReturn
|
|
io.imem.ras_update.bits.prediction := io.imem.btb_update.bits.prediction
|
|
|
|
io.fpu.valid := !ctrl_killd && id_ctrl.fp
|
|
io.fpu.killx := ctrl_killx
|
|
io.fpu.killm := killm_common
|
|
io.fpu.inst := id_inst
|
|
io.fpu.fromint_data := ex_rs(0)
|
|
io.fpu.dmem_resp_val := dmem_resp_valid && dmem_resp_fpu
|
|
io.fpu.dmem_resp_data := io.dmem.resp.bits.data_word_bypass
|
|
io.fpu.dmem_resp_type := io.dmem.resp.bits.typ
|
|
io.fpu.dmem_resp_tag := dmem_resp_waddr
|
|
|
|
io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem
|
|
val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)
|
|
require(coreDCacheReqTagBits >= ex_dcache_tag.getWidth)
|
|
io.dmem.req.bits.tag := ex_dcache_tag
|
|
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
|
|
io.dmem.req.bits.typ := ex_ctrl.mem_type
|
|
io.dmem.req.bits.phys := Bool(false)
|
|
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
|
|
io.dmem.s1_kill := killm_common || mem_xcpt
|
|
io.dmem.s1_data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
|
|
io.dmem.invalidate_lr := wb_xcpt
|
|
|
|
io.rocc.cmd.valid := wb_rocc_val
|
|
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
|
|
io.rocc.status := csr.io.status
|
|
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
|
|
io.rocc.cmd.bits.rs1 := wb_reg_wdata
|
|
io.rocc.cmd.bits.rs2 := wb_reg_rs2
|
|
|
|
if (enableCommitLog) {
|
|
val pc = Wire(SInt(width=xLen))
|
|
pc := wb_reg_pc
|
|
val inst = wb_reg_inst
|
|
val rd = RegNext(RegNext(RegNext(id_waddr)))
|
|
val wfd = wb_ctrl.wfd
|
|
val wxd = wb_ctrl.wxd
|
|
val has_data = wb_wen && !wb_set_sboard
|
|
val priv = csr.io.status.prv
|
|
|
|
when (wb_valid) {
|
|
when (wfd) {
|
|
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd+UInt(32))
|
|
}
|
|
.elsewhen (wxd && rd =/= UInt(0) && has_data) {
|
|
printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, inst, rd, rf_wdata)
|
|
}
|
|
.elsewhen (wxd && rd =/= UInt(0) && !has_data) {
|
|
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, inst, rd, rd)
|
|
}
|
|
.otherwise {
|
|
printf ("%d 0x%x (0x%x)\n", priv, pc, inst)
|
|
}
|
|
}
|
|
|
|
when (ll_wen && rf_waddr =/= UInt(0)) {
|
|
printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
|
|
}
|
|
}
|
|
else {
|
|
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
|
|
io.prci.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
|
|
Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
|
|
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
|
|
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
|
|
wb_reg_inst, wb_reg_inst)
|
|
}
|
|
|
|
def checkExceptions(x: Seq[(Bool, UInt)]) =
|
|
(x.map(_._1).reduce(_||_), PriorityMux(x))
|
|
|
|
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
|
|
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
|
|
|
|
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
|
|
// efficient means to compress 64-bit VA into vaddrBits+1 bits
|
|
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
|
|
val a = a0 >> vaddrBits-1
|
|
val e = ea(vaddrBits,vaddrBits-1).toSInt
|
|
val msb =
|
|
Mux(a === UInt(0) || a === UInt(1), e =/= SInt(0),
|
|
Mux(a.toSInt === SInt(-1) || a.toSInt === SInt(-2), e === SInt(-1), e(0)))
|
|
Cat(msb, ea(vaddrBits-1,0))
|
|
}
|
|
|
|
class Scoreboard(n: Int)
|
|
{
|
|
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
|
|
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
|
|
def read(addr: UInt): Bool = r(addr)
|
|
def readBypassed(addr: UInt): Bool = _next(addr)
|
|
|
|
private val r = Reg(init=Bits(0, n))
|
|
private var _next = r
|
|
private var ens = Bool(false)
|
|
private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
|
|
private def update(en: Bool, update: UInt) = {
|
|
_next = update
|
|
ens = ens || en
|
|
when (ens) { r := _next }
|
|
}
|
|
}
|
|
}
|