Andrew Waterman
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6e540825b2
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Use entire 12-bit CSR address
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2015-03-14 02:15:24 -07:00 |
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Yunsup Lee
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ebbd14254c
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uncached port should be a HeaderlessUncachedTileLinkIO type
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2015-03-13 02:12:23 -07:00 |
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Yunsup Lee
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3a78ca210d
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bugfix in uncached TL to TL convertors
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2015-03-12 16:33:41 -07:00 |
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Henry Cook
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51e4cd7616
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Added UncachedTileLinkIO port to RocketTile, simplify arbitration
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2015-03-12 16:30:04 -07:00 |
|
Henry Cook
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8181262419
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clean up incoherent and probe flags
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2015-03-12 16:22:14 -07:00 |
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Henry Cook
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dcc84c4dd3
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arbiter probe ready bugfix
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2015-03-12 16:02:51 -07:00 |
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Yunsup Lee
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2c31ed6426
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previous bug fix for meta data writeback wasn't quite right
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2015-03-12 15:34:20 -07:00 |
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Yunsup Lee
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5e40c8ba77
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write back meta data when cache miss even when coherence meta data is clean
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2015-03-12 14:36:46 -07:00 |
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Albert Ou
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8f8022379c
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Fix AMO opcode extraction
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2015-03-11 23:24:58 -07:00 |
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Albert Ou
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f75126c39c
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Require self probes for all built-in Acquire types
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
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2015-03-11 23:24:58 -07:00 |
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Yunsup Lee
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ea018b3d84
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stall rocket decode when not rocc ready
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2015-03-11 22:33:03 -07:00 |
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Henry Cook
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1aff919c24
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added prefetchAck Grant type
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2015-03-11 17:32:06 -07:00 |
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Henry Cook
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059575c334
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cleanup mergeData and prep for cleaner data_buffer in L2
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2015-03-11 15:43:41 -07:00 |
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Henry Cook
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b4ed1d9121
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Add builtin prefetch types to TileLink
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2015-03-11 14:28:17 -07:00 |
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Yunsup Lee
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3ab1aca7de
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L2 subblock access bugfix
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2015-03-11 01:56:47 -07:00 |
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Colin Schmidt
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e293d89035
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fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
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2015-03-10 10:28:05 -07:00 |
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Henry Cook
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17072a0041
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L2 Writeback bugfix
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2015-03-10 01:15:03 -07:00 |
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Henry Cook
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a1f04386f7
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Headerless TileLinkIO and arbiters
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2015-03-09 16:34:59 -07:00 |
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Henry Cook
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95aa295c39
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Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
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2015-03-09 16:34:43 -07:00 |
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Henry Cook
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002f1a1b39
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pin outer finish header
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2015-03-09 12:40:37 -07:00 |
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Henry Cook
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df79e7ff8d
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secondary miss bug
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2015-03-05 15:51:18 -08:00 |
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Henry Cook
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8e41fcf6fc
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reduce MemIFTag size, enable non pow2 HellaFLowQueue size
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2015-03-05 15:51:02 -08:00 |
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Henry Cook
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b36d751250
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sret bugfix: bypass arbiter
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2015-03-05 13:14:16 -08:00 |
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Henry Cook
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35532420a8
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Merge pull request #6 from ccelio/master
Clarified ptw/tlb/sret/cache I/O bundles
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2015-03-03 18:01:26 -08:00 |
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Christopher Celio
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06dea3790a
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Removed sret from ptw; sret now comes thru io.cpu to dcache
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2015-03-03 16:50:41 -08:00 |
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Christopher Celio
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5d07733057
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Removed TLBPTWIO from the io.cpu bundle for icache/dcache
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2015-03-03 16:40:39 -08:00 |
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Henry Cook
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1bed6ea498
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New metadata-based coherence API
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2015-02-28 17:32:03 -08:00 |
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Henry Cook
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1e0c16c557
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new metadata api
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2015-02-28 17:00:32 -08:00 |
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Yunsup Lee
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4f57985198
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change organization to riscv
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2015-02-17 14:43:11 -08:00 |
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Henry Cook
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0a8722e881
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bugfix for indexing DataArray of of small L2
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2015-02-17 00:37:40 -08:00 |
|
Henry Cook
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0b131173e6
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WritebackUnit multibeat control logic bugfix
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2015-02-16 10:59:57 -08:00 |
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Henry Cook
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0c66e70f14
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cleanup of conflicts; allocation bugfix
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2015-02-06 13:20:44 -08:00 |
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Albert Magyar
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09cd555f29
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Update riscv-tools pointer to prepare for HPCA workshop.
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2015-02-04 13:29:04 -08:00 |
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Henry Cook
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7b86ea17cf
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rename L2HellaCache to L2HellaCacheBank
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2015-02-03 19:38:01 -08:00 |
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Henry Cook
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aa46b8b72d
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Slightly refactor TLBResp
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2015-02-03 19:32:37 -08:00 |
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Stephen Twigg
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3b3250339a
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Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
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2015-02-03 18:15:01 -08:00 |
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Stephen Twigg
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3d35ccd401
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Explicitely convert results of Bits Muxes to UInt
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
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2015-02-03 18:10:54 -08:00 |
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Henry Cook
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57340be72b
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doc update
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2015-02-02 01:11:13 -08:00 |
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Henry Cook
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6141b3efc5
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uncached -> builtin_type
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2015-02-02 01:02:06 -08:00 |
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Henry Cook
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e6491d351f
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Offset AMOs within beat and return old value
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2015-02-02 00:22:21 -08:00 |
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Henry Cook
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741e6b77ad
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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Henry Cook
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3aa030f960
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Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
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2015-02-01 20:37:16 -08:00 |
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Henry Cook
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7b4e9dd137
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Block L2 transactions on the same set from proceeding in parallel
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2015-02-01 20:29:23 -08:00 |
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Henry Cook
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973eb43128
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state machine bug on uncached write hits
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2015-02-01 20:29:23 -08:00 |
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Scott Beamer
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00e074cdd9
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fixes slight bug for non-power of 2 number of ras entries
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2015-01-29 15:29:25 -08:00 |
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Henry Cook
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f58f8bf385
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Make L2 data array use a single Mem
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2015-01-25 15:37:04 -08:00 |
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Scott Beamer
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2a5dd907f5
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bump chisel version
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2015-01-06 16:59:10 -08:00 |
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Andrew Waterman
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a98127c09e
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Merge branch 'ss-frontend'
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2015-01-04 20:26:38 -08:00 |
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Andrew Waterman
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b70f7683d3
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Merge branch 'master' into ss-frontend
Conflicts:
src/main/scala/ctrl.scala
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2015-01-04 19:59:18 -08:00 |
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Andrew Waterman
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87ad1a5703
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More control cleanup
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2015-01-04 19:46:01 -08:00 |
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