riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
7b86ea17cf rename L2HellaCache to L2HellaCacheBank 2015-02-03 19:38:01 -08:00
Henry Cook
aa46b8b72d Slightly refactor TLBResp 2015-02-03 19:32:37 -08:00
Stephen Twigg
3b3250339a Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:15:01 -08:00
Stephen Twigg
3d35ccd401 Explicitely convert results of Bits Muxes to UInt 
Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
 2015-02-03 18:10:54 -08:00
Henry Cook
57340be72b doc update 2015-02-02 01:11:13 -08:00
Henry Cook
6141b3efc5 uncached -> builtin_type 2015-02-02 01:02:06 -08:00
Henry Cook
e6491d351f Offset AMOs within beat and return old value 2015-02-02 00:22:21 -08:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel 2015-02-01 20:29:23 -08:00
Henry Cook
973eb43128 state machine bug on uncached write hits 2015-02-01 20:29:23 -08:00
Scott Beamer
00e074cdd9 fixes slight bug for non-power of 2 number of ras entries 2015-01-29 15:29:25 -08:00
Henry Cook
f58f8bf385 Make L2 data array use a single Mem 2015-01-25 15:37:04 -08:00
Scott Beamer
2a5dd907f5 bump chisel version 2015-01-06 16:59:10 -08:00
Andrew Waterman
a98127c09e Merge branch 'ss-frontend' 2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3 Merge branch 'master' into ss-frontend 
Conflicts:
	src/main/scala/ctrl.scala
 2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703 More control cleanup 2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11 Flush pipeline from MEM stage 
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control.  But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
 2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1 Continue refactoring control 2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9 Much refactor, so control 2015-01-03 13:34:38 -08:00
Henry Cook
1cb65d5ec1 %s/master/manager/g 2014-12-29 22:56:18 -08:00
Henry Cook
9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook
c76b4bc21d TileLink doc 2014-12-29 22:55:18 -08:00
Henry Cook
e62c71203e disconnect unused outer network headers 2014-12-22 18:50:37 -08:00
Henry Cook
2ef4357ca8 acquire allocation bugfix 2014-12-19 17:39:23 -08:00
Henry Cook
f234fe65ce Initial verison of L2WritebackUnit, passes MiT2 bmark tests 2014-12-19 03:03:53 -08:00
Henry Cook
d121af7f94 Simplify release handling 2014-12-18 17:12:29 -08:00
Henry Cook
77e5e6b561 refill bug 2014-12-17 19:29:28 -08:00
Henry Cook
bfcfc3fe18 refactor cache params 2014-12-17 14:28:14 -08:00
Henry Cook
08dcf4c6ca refactor cache params 2014-12-17 14:28:05 -08:00
Henry Cook
ab39cbb15d cleanup DirectoryRepresentation and coherence params 2014-12-15 19:24:42 -08:00
Henry Cook
d29793d1f7 cleanup CoherenceMetadata and coherence params 2014-12-15 19:23:38 -08:00
Andrew Waterman
d04da83f96 Make data RAMs 1RW instead of 1R1W 2014-12-15 17:36:17 -08:00
Henry Cook
6a8b66231c Add uncached->cached tilelink converter 2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f 1R/W L2 data array? 
Add TLDataBeats to new LLC; all bmarks pass
 2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db Begin adding TLDataBeats to uncore 2014-12-12 17:04:31 -08:00
Henry Cook
c9320862ae add l2 dmem signal to rocc 2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b multibeat TL; passes all tests 2014-12-12 16:54:33 -08:00
Henry Cook
404773eb9f fix wb bug 2014-12-03 14:22:39 -08:00
Henry Cook
05b5188ad9 meta and data bundle refactor 2014-11-19 15:55:25 -08:00
Christopher Celio
f19b3ca43e Deleted extra spaces at EOL in ctrl.scala 2014-11-16 22:04:33 -08:00
Christopher Celio
6749f67b7f Fixed BHT update error. 
- separated out BTB/BHT update
   - BHT updates counters on every branch
   - BTB update only on mispredicted and taken branches
 2014-11-16 22:02:27 -08:00
Henry Cook
a519a43f23 Merge branch 'master' into new-llc 
Conflicts:
	src/main/scala/coherence.scala
	src/main/scala/memserdes.scala
	src/main/scala/tilelink.scala
 2014-11-12 16:25:25 -08:00
Henry Cook
cb7e712599 Added uncached write data queue to coherence hub 2014-11-12 12:55:07 -08:00
Henry Cook
b7b2923bff Cleanup MSHR internal bundles 2014-11-11 18:18:35 -08:00
Henry Cook
82155f333e Major tilelink revision for uncached message types 2014-11-11 17:36:55 -08:00
Henry Cook
c9e7874818 Major tilelink revision for uncached message types 2014-11-11 17:36:48 -08:00
Henry Cook
35553cc0b7 NullDirectory sharers.count fix 2014-11-11 16:05:25 -08:00
Christopher Celio
fea31d2167 Significant changes and fixes to BTB for superscalar fetch. 
- BTBUpdate only occurs on mispredicts now.
   - RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
      Decode).
   - Added optional 2nd CAM port to BTB for updates (for when updates to the
      BTB may occur out-of-order).
   - Fixed resp.mask bit logic.
 2014-11-11 03:34:05 -08:00