Stephen Twigg
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2676ea8279
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Push rocket (fix some issues with RoCC although some remain)
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2013-09-22 03:19:43 -07:00 |
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Stephen Twigg
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158cee08af
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Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
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2013-09-22 03:18:06 -07:00 |
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Andrew Waterman
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b7d7ced41b
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Update to new ISA
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2013-09-21 06:40:23 -07:00 |
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Andrew Waterman
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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Huy Vo
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09247c0e0b
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fix to sram init pins
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2013-09-19 20:12:10 -07:00 |
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Huy Vo
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c9813603ee
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Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
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2013-09-19 20:11:11 -07:00 |
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Huy Vo
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cc3dc1bd0f
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bug fix
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2013-09-19 20:10:56 -07:00 |
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Andrew Waterman
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9bf10ae5d2
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remove extraneous toBits (need new Chisel)
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2013-09-19 15:26:36 -07:00 |
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Andrew Waterman
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42970c9a99
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Update Rocket
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2013-09-15 04:39:52 -07:00 |
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Andrew Waterman
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25ab402932
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swap JAL, JALR encodings
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2013-09-15 04:29:06 -07:00 |
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Andrew Waterman
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628745226c
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Use spike disassembler riscv-dis if it exists
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2013-09-15 04:25:53 -07:00 |
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Andrew Waterman
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80003b3019
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Support RoCC
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2013-09-15 04:25:26 -07:00 |
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Andrew Waterman
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110e53cb48
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Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
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2013-09-15 04:15:32 -07:00 |
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Andrew Waterman
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88d1c47665
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don't disassemble within chisel
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2013-09-15 04:14:45 -07:00 |
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Andrew Waterman
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
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Andrew Waterman
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18968dfbc7
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Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
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Andrew Waterman
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
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Andrew Waterman
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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Andrew Waterman
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1edb1e2a0a
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Ignore LSB of PC
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2013-09-12 17:55:58 -07:00 |
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Andrew Waterman
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fbdbb01232
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update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
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Andrew Waterman
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cc7783404d
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Add memory command M_XA_XOR
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2013-09-12 16:09:53 -07:00 |
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Andrew Waterman
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59f5358435
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Implement AQ/RL; move fence logic out of cache
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2013-09-12 16:07:30 -07:00 |
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Andrew Waterman
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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Andrew Waterman
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95dd0d8be1
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Remove DebugIO/error mode
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2013-09-11 20:15:21 -07:00 |
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Henry Cook
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b42e140e05
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NetworkIOs no longer use thunks
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2013-09-10 16:23:52 -07:00 |
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Henry Cook
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1cac26fd76
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NetworkIOs no longer use thunks
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2013-09-10 16:15:41 -07:00 |
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Henry Cook
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f9b85d8158
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NetworkIOs no longer use thunks
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2013-09-10 16:15:19 -07:00 |
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Henry Cook
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ee98cd8378
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new enum syntax
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2013-09-10 10:54:51 -07:00 |
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Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Stephen Twigg
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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Stephen Twigg
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e23e8e3850
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/memserdes.scala
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2013-09-05 16:17:34 -07:00 |
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Stephen Twigg
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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Stephen Twigg
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f27c0fb010
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Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2
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2013-09-05 15:01:56 -07:00 |
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Stephen Twigg
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69daae0dae
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Add dependency resolvers to build.scala to fix build script
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2013-09-05 14:56:41 -07:00 |
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Yunsup Lee
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2c47b4388a
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push rocket
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2013-08-26 14:54:49 -07:00 |
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Andrew Waterman
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
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Yunsup Lee
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9003bc2614
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push rocket
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2013-08-24 22:42:57 -07:00 |
|
Yunsup Lee
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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Yunsup Lee
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d0674af13f
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forgot to push riscv-rocket
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2013-08-24 22:15:38 -07:00 |
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Andrew Waterman
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
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Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
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Yunsup Lee
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76cd90fc01
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parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
|
Yunsup Lee
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2ca5127785
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parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
|
Yunsup Lee
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694ebd65cf
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push uncore
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2013-08-24 15:24:25 -07:00 |
|
Yunsup Lee
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b01fe4f6aa
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fix memserdes bit ordering
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2013-08-24 15:24:17 -07:00 |
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Andrew Waterman
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daf23b8f79
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Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
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Andrew Waterman
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
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Andrew Waterman
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
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Andrew Waterman
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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