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Commit Graph

3357 Commits

Author SHA1 Message Date
Stephen Twigg
2676ea8279 Push rocket (fix some issues with RoCC although some remain) 2013-09-22 03:19:43 -07:00
Stephen Twigg
158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) 2013-09-22 03:18:06 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Huy Vo
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Huy Vo
c9813603ee Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 2013-09-19 20:11:11 -07:00
Huy Vo
cc3dc1bd0f bug fix 2013-09-19 20:10:56 -07:00
Andrew Waterman
9bf10ae5d2 remove extraneous toBits (need new Chisel) 2013-09-19 15:26:36 -07:00
Andrew Waterman
42970c9a99 Update Rocket 2013-09-15 04:39:52 -07:00
Andrew Waterman
25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
Andrew Waterman
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman
110e53cb48 Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451 Start adding RoCC 2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
1edb1e2a0a Ignore LSB of PC 2013-09-12 17:55:58 -07:00
Andrew Waterman
fbdbb01232 update to new isa; disable vector tests 2013-09-12 17:04:03 -07:00
Andrew Waterman
cc7783404d Add memory command M_XA_XOR 2013-09-12 16:09:53 -07:00
Andrew Waterman
59f5358435 Implement AQ/RL; move fence logic out of cache 2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342 sync up rocket with new isa 2013-09-12 03:44:38 -07:00
Andrew Waterman
95dd0d8be1 Remove DebugIO/error mode 2013-09-11 20:15:21 -07:00
Henry Cook
b42e140e05 NetworkIOs no longer use thunks 2013-09-10 16:23:52 -07:00
Henry Cook
1cac26fd76 NetworkIOs no longer use thunks 2013-09-10 16:15:41 -07:00
Henry Cook
f9b85d8158 NetworkIOs no longer use thunks 2013-09-10 16:15:19 -07:00
Henry Cook
ee98cd8378 new enum syntax 2013-09-10 10:54:51 -07:00
Henry Cook
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00
Stephen Twigg
6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Stephen Twigg
cfbfa6b895 Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits. 2013-09-05 19:22:34 -07:00
Stephen Twigg
e23e8e3850 Merge branch 'master' into chisel-v2
Conflicts:
	src/main/scala/memserdes.scala
2013-09-05 16:17:34 -07:00
Stephen Twigg
d896ccbd43 Merge branch 'master' into chisel-v2
Conflicts:
	src/main/scala/htif.scala
2013-09-05 16:11:53 -07:00
Stephen Twigg
f27c0fb010 Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2 2013-09-05 15:01:56 -07:00
Stephen Twigg
69daae0dae Add dependency resolvers to build.scala to fix build script 2013-09-05 14:56:41 -07:00
Yunsup Lee
2c47b4388a push rocket 2013-08-26 14:54:49 -07:00
Andrew Waterman
b9f6e1a7ec Don't update BTB when garbage was fetched 2013-08-26 14:53:04 -07:00
Yunsup Lee
9003bc2614 push rocket 2013-08-24 22:42:57 -07:00
Yunsup Lee
44e92edf92 fix scr parameterization bug 2013-08-24 22:42:51 -07:00
Yunsup Lee
d0674af13f forgot to push riscv-rocket 2013-08-24 22:15:38 -07:00
Andrew Waterman
3895b75a56 Support non-power-of-2 BTBs; prefer invalid entries 2013-08-24 17:33:11 -07:00
Yunsup Lee
ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee
76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee
2ca5127785 parameterize number of SCRs 2013-08-24 15:47:14 -07:00
Yunsup Lee
694ebd65cf push uncore 2013-08-24 15:24:25 -07:00
Yunsup Lee
b01fe4f6aa fix memserdes bit ordering 2013-08-24 15:24:17 -07:00
Andrew Waterman
daf23b8f79 Add early out to multiplier 2013-08-24 14:44:23 -07:00
Andrew Waterman
67f80ba4b2 Stall div/mul writeback until WB slot is free 2013-08-24 14:44:17 -07:00
Andrew Waterman
d1b5076fee Don't update BTB when garbage was fetched 2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298 Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
2013-08-24 14:44:04 -07:00