Henry Cook
7d6a642c0c
correct use of function value to initialize MetaDataArray
2014-05-06 13:00:00 -07:00
Henry Cook
7f690dd9c8
parameterize metadataarray
2014-05-01 01:45:45 -07:00
Henry Cook
519b2ea2b6
New metadata result trait
2014-04-26 19:08:56 -07:00
Henry Cook
1b156c6db9
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:18:21 -07:00
Henry Cook
fc825c7103
MetaData & friends moved to uncore/
2014-04-23 16:23:51 -07:00
Henry Cook
f4d326b8d7
Prep in HellaCache for extracting MetaData to uncore
2014-04-23 15:43:31 -07:00
Henry Cook
5c62cff2ce
put replacement policy in uncore and minor nbdcache cleanups
2014-04-22 16:53:20 -07:00
Andrew Waterman
09e2ec1f9e
Fix sign of remainder when dividing by zero
...
h/t chris
2014-04-18 16:32:57 -07:00
Henry Cook
1fa505f9ff
remove superfluous AVec object
2014-04-16 17:19:32 -07:00
Andrew Waterman
3520620fbd
Remove D$ -> BTB path
2014-04-15 23:05:02 -07:00
Andrew Waterman
de492b3cf7
Fix critical path through integer scoreboard
2014-04-15 21:28:13 -07:00
Henry Cook
444d0449e3
io.cnt bug in serializer
2014-04-14 17:13:13 -07:00
Henry Cook
1da8ef2ddf
Added serdes to decouple cache row size from tilelink data size
2014-04-10 12:34:12 -07:00
Henry Cook
910b3b203a
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:32:44 -07:00
Henry Cook
ebdc0a2692
merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
2014-04-10 12:09:52 -07:00
Stephen Twigg
e90f2484aa
Sync with riscv-opcodes (csr register mapping)
2014-04-08 15:48:37 -07:00
Andrew Waterman
3ed8adf032
Add early out for MUL[W] (not MULH[[S]U])
2014-04-07 23:48:02 -07:00
Andrew Waterman
927287da34
Bypass RAS push/pop
2014-04-07 23:47:53 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
db59fc65ab
Add return address stack
2014-04-01 15:01:27 -07:00
Andrew Waterman
e3b12e0b85
Make BTB more complexity-effective
...
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
2014-03-25 05:22:04 -07:00
Andrew Waterman
804b09c8c5
Frontend QoR tweaks
2014-03-25 05:20:24 -07:00
Andrew Waterman
6465e2df14
Make Int -> Bool conversions explicit
2014-03-24 04:36:53 -07:00
Andrew Waterman
1b030777ce
Remove vestigial control signal
2014-03-24 04:36:12 -07:00
Andrew Waterman
5996418021
Fix exception behavior of fmin/fmax
2014-03-18 18:36:51 -07:00
Andrew Waterman
54cbf0c4f1
Add (unused) RV32 CSRs
2014-03-15 17:33:17 -07:00
Andrew Waterman
943d7ac80a
Use LinkedHashSet/Map for simpler determinism
2014-03-15 17:31:48 -07:00
Donggyu Kim
53d62cb69d
remove nondeterminism
2014-03-15 16:45:58 -07:00
Andrew Waterman
a0389645b7
New FP encoding; improved FP implementation
2014-03-11 18:58:24 -07:00
Andrew Waterman
00bc1a2293
Add fclass.{s|d} instructions
2014-03-10 16:59:24 -07:00
Yunsup Lee
ac4b3f9f22
print out core id
2014-03-04 23:38:49 -08:00
Andrew Waterman
9f2e16c58a
Fix D$ arbiter for >2 inputs
2014-03-04 16:32:17 -08:00
Andrew Waterman
fa75f6e81e
Fix null pointer exception when HAS_FPU=false
2014-03-04 16:32:09 -08:00
Andrew Waterman
c7110c8389
Make FPU pipeline depths configurable
2014-02-28 13:39:59 -08:00
Yunsup Lee
98b830201a
add wen signal to dasm printf
2014-02-25 03:31:06 -08:00
Yunsup Lee
97b1841fcf
change dcache tag bits to 7
2014-02-22 22:53:04 -08:00
Andrew Waterman
8e3ca609f7
Renumber uarch CSRs into custom CSR space
2014-02-14 17:40:00 -08:00
Andrew Waterman
a09ff9fdc7
Revert to old AUIPC definition
2014-02-10 19:04:42 -08:00
Andrew Waterman
1456170c6d
Always stall decode on RoCC -> FENCE; never stall on RoCC -> deferred AMO.RL fence
2014-02-06 12:01:49 -08:00
Andrew Waterman
eca8c99f44
Ignore rocc interrupt line when no rocc is present
2014-02-06 03:06:55 -08:00
Andrew Waterman
e7a726fbac
Make uarch counters read-only
2014-02-06 01:48:56 -08:00
Quan Nguyen
f021213b1d
Merge remote-tracking branch 'origin/master' into hwacha-port
2014-02-06 00:21:28 -08:00
Andrew Waterman
62e9313aef
Add 16 microarchitectural counters
2014-02-06 00:13:02 -08:00
Yunsup Lee
ff7cae29f7
hookup rocc interrupt and s bit
2014-02-06 00:09:42 -08:00
Yunsup Lee
ab4a3e937b
don't share fma pipes
2014-02-05 14:21:43 -08:00
Stephen Twigg
6a02d15c21
Merge branch 'master' into hwacha-port
2014-02-04 17:05:03 -08:00
Henry Cook
2c2b3a7678
cleanups supporting uncore hierarchy
2014-01-31 12:07:26 -08:00
Andrew Waterman
febd26f505
Correct CSR privilege logic
2014-01-31 01:03:17 -08:00
Stephen Twigg
3c3c469725
Add exception signal to rocc interface
2014-01-28 22:13:16 -08:00
Andrew Waterman
0266c1f76a
Support retirement width > 1 in CSR file
2014-01-24 16:37:40 -08:00
Andrew Waterman
267394d3cc
Fix CSR interlocks
2014-01-24 16:37:40 -08:00
Andrew Waterman
1f986d1c96
Branches don't care about the ALU input/function
2014-01-24 16:37:40 -08:00
Andrew Waterman
a1b7774f5d
Simplify handling of CAUSE register
2014-01-24 16:37:39 -08:00
Christopher Celio
a2be21361e
Allow ICacheConfig to toggle fetch-width.
2014-01-22 16:19:57 -08:00
Andrew Waterman
a7489920ce
Support CSR atomics on all CSRs, not just STATUS
2014-01-21 16:17:39 -08:00
Andrew Waterman
6ba2c1abe5
Use auto-generated CAUSE constants
2014-01-21 15:01:54 -08:00
Andrew Waterman
95de358a96
More of the same FPU fix
...
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98
Fix fmv.s.x -> fsd
2014-01-17 03:52:35 -08:00
Yunsup Lee
30b894c2c4
Merge remote-tracking branch 'origin/master' into hwacha-port
2014-01-16 16:04:48 -08:00
Yunsup Lee
6bbbf36979
push accel/rocket dmem port back to rocket
2014-01-16 16:01:41 -08:00
Andrew Waterman
57f4d89c90
Generate D$ replay_next signals correctly
2014-01-16 00:16:09 -08:00
Andrew Waterman
6ebdc4d94e
Simplify store conditional failure code generation
2014-01-16 00:15:48 -08:00
Andrew Waterman
31060ea8ae
Fix fubar long-latency writeback control logic
...
Load miss writebacks happening at the same time as multiplication
wasn't working. Hopefully this does it.
2014-01-14 04:02:43 -08:00
Andrew Waterman
e8486817e6
Clean up formatting (i.e. remove tabs, semicolons)
2014-01-13 21:43:56 -08:00
Andrew Waterman
a50a1f7d50
Clean up multiplier/divider stuff
2014-01-13 21:37:16 -08:00
Andrew Waterman
4d236979bd
Fix very far forward JALs
...
We were sign-extending from the wrong bit, causing a backwards jump.
2014-01-13 00:55:48 -08:00
Andrew Waterman
c546f66404
Swap JAL/JALR encodings (again)
2014-01-13 00:54:49 -08:00
Quan Nguyen
ebec444ad2
Increase tag width for configurable precision in Hwacha
2013-12-13 03:33:02 -08:00
Andrew Waterman
07a91bb99a
Miscellaneous cleanup
2013-12-09 19:53:14 -08:00
Andrew Waterman
da3135ac9b
Begin integer unit clean-up
...
...to make it easier to generate the superscalar version of the core.
2013-12-09 15:06:13 -08:00
Andrew Waterman
16d5250924
Correct FP trap behavior on FCSR
2013-12-05 04:18:04 -08:00
Andrew Waterman
5814a90472
Make DecodeLogic interface more flexible
2013-12-05 04:16:48 -08:00
Andrew Waterman
924261e2b2
Update to new privileged ISA... phew
2013-11-25 04:35:15 -08:00
Andrew Waterman
65b8340cea
Mitigate D$ hit -> branch -> NPC critical path
2013-11-24 14:21:03 -08:00
Andrew Waterman
53f726008b
Use Mem instead of Vec[Reg] for TLB
...
QoR-neutral, improves simulation speed
2013-11-24 14:21:02 -08:00
Yunsup Lee
d450b85483
Merge branch 'master', remote-tracking branch 'origin' into hwacha
2013-11-21 14:57:38 -08:00
Yunsup Lee
68e270eeb2
fix slli/slliw encoding bug
2013-11-21 14:44:58 -08:00
Quan Nguyen
3b109763ad
Connect FMA to Hwacha pipes
2013-11-19 20:54:47 -08:00
Stephen Twigg
a662e85f2a
Merge branch 'master' into hwacha
2013-11-14 16:02:44 -08:00
Yunsup Lee
c1966e2b0a
forgot to put htif into uncore package
2013-11-07 15:42:03 -08:00
Yunsup Lee
da033af0b0
move htif to uncore
2013-11-07 13:18:46 -08:00
Yunsup Lee
4c56323f6f
hookup all memory ports
2013-11-05 17:12:09 -08:00
Stephen Twigg
eae571e371
Remove rocc memory simplifye module (Hwacha has its own)
2013-11-05 15:31:03 -08:00
Andrew Waterman
12f0369e6e
Simplify divide early out circuitry
2013-10-29 13:20:40 -07:00
Andrew Waterman
b44dafbdca
Simplify branch offset mux
2013-10-29 13:20:40 -07:00
Andrew Waterman
23f7bab4f3
Reduce FMA pipeline depths
...
FMA QoR has improved enough to allow this change.
2013-10-29 13:20:40 -07:00
Yunsup Lee
1583560757
fix replay bug, don't respond when cmd is a NOP
2013-10-28 22:35:18 -07:00
Stephen Twigg
36b85b8ee2
Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached.
2013-09-25 11:51:10 -07:00
Stephen Twigg
891e459625
Export stats pcr register ( #28 currently) to the top-level
2013-09-25 01:16:32 -07:00
Stephen Twigg
730a6ec76b
AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample
2013-09-24 16:32:49 -07:00
Andrew Waterman
81c752de84
Support disabling virtual memory
2013-09-24 13:58:47 -07:00
Andrew Waterman
adc386f889
Turn off virtual memory inside RoCC base class
2013-09-24 13:58:47 -07:00
Stephen Twigg
3532ae0b79
From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).
2013-09-24 10:54:09 -07:00
Stephen Twigg
db1e09f0d0
Fix issues with RoCC AccumulatorExample stalls on memory interface
2013-09-23 00:21:43 -07:00
Stephen Twigg
158cee08af
Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)
2013-09-22 03:18:06 -07:00
Andrew Waterman
1d2f4f8437
New ISA encoding, AUIPC semantics
2013-09-21 06:32:40 -07:00
Andrew Waterman
25ab402932
swap JAL, JALR encodings
2013-09-15 04:29:06 -07:00
Andrew Waterman
110e53cb48
Revert "Add early out to multiplier"
...
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665
don't disassemble within chisel
2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43
working RoCC AccumulatorExample
2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7
Move store data generation into cache
2013-09-14 16:15:07 -07:00
Andrew Waterman
a0cb711451
Start adding RoCC
2013-09-14 15:31:50 -07:00
Andrew Waterman
d053bdc89f
Remove Hwacha from Rocket
...
Soon it will use the coprocessor interface.
2013-09-12 22:34:38 -07:00
Andrew Waterman
1edb1e2a0a
Ignore LSB of PC
2013-09-12 17:55:58 -07:00
Andrew Waterman
59f5358435
Implement AQ/RL; move fence logic out of cache
2013-09-12 16:07:30 -07:00
Andrew Waterman
243c4ae342
sync up rocket with new isa
2013-09-12 03:44:38 -07:00
Andrew Waterman
95dd0d8be1
Remove DebugIO/error mode
2013-09-11 20:15:21 -07:00
Henry Cook
f9b85d8158
NetworkIOs no longer use thunks
2013-09-10 16:15:19 -07:00
Henry Cook
d06e24ac24
new enum syntax
2013-09-10 10:51:35 -07:00
Stephen Twigg
cfbfa6b895
Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
2013-09-05 19:22:34 -07:00
Stephen Twigg
d896ccbd43
Merge branch 'master' into chisel-v2
...
Conflicts:
src/main/scala/htif.scala
2013-09-05 16:11:53 -07:00
Andrew Waterman
b9f6e1a7ec
Don't update BTB when garbage was fetched
2013-08-26 14:53:04 -07:00
Yunsup Lee
44e92edf92
fix scr parameterization bug
2013-08-24 22:42:51 -07:00
Andrew Waterman
3895b75a56
Support non-power-of-2 BTBs; prefer invalid entries
2013-08-24 17:33:11 -07:00
Yunsup Lee
2ca5127785
parameterize number of SCRs
2013-08-24 15:47:14 -07:00
Andrew Waterman
daf23b8f79
Add early out to multiplier
2013-08-24 14:44:23 -07:00
Andrew Waterman
67f80ba4b2
Stall div/mul writeback until WB slot is free
2013-08-24 14:44:17 -07:00
Andrew Waterman
d1b5076fee
Don't update BTB when garbage was fetched
2013-08-24 14:44:11 -07:00
Andrew Waterman
52e31f3298
Bypass scoreboard updates
...
This reduces div/mul/D$ miss latency by 1 cycle.
2013-08-24 14:44:04 -07:00
Andrew Waterman
d4a0db4575
Reflect ISA changes
2013-08-24 14:43:55 -07:00
Henry Cook
ff7b486006
standardized sbt build
2013-08-15 18:13:19 -07:00
Henry Cook
ae02ebd153
Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
...
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
2013-08-15 16:35:27 -07:00
Henry Cook
3a266cbbfa
final Reg changes
2013-08-15 15:28:15 -07:00
Henry Cook
b570435847
Reg standardization
2013-08-13 17:50:02 -07:00
Henry Cook
858169917e
removed dummy DNCs handled by pruning
2013-08-12 22:34:46 -07:00
Henry Cook
d9b3c7cfc8
Moved RenEn to ChiselUtil
2013-08-12 22:18:25 -07:00
Huy Vo
387cf0ebe0
reset -> resetVal, getReset -> reset
2013-08-12 20:51:54 -07:00
Henry Cook
1a9e43aa11
initial attempt at upgrade
2013-08-12 10:39:11 -07:00
Henry Cook
de313d97de
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2013-08-02 16:30:09 -07:00
Henry Cook
4eaab214d2
Fold uncore constants into TileLinkConfiguration, update coherence API
2013-08-02 16:29:51 -07:00
Henry Cook
bef6c1db35
minor nbdcache cleanup
2013-08-02 16:29:37 -07:00
Stephen Twigg
3132db4f90
Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
2013-07-30 16:36:28 -07:00
Henry Cook
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
2013-07-23 20:27:58 -07:00
Henry Cook
5c00d0a030
new tilelink arbiter type
2013-07-09 15:31:46 -07:00
Andrew Waterman
7cc53c7725
clean up Str
2013-06-15 00:45:53 -07:00
Andrew Waterman
95c5147dc5
Add RISC-V instruction disassembler
2013-06-13 10:31:04 -07:00
Henry Cook
569d8fd796
Merge branch 'tilelink-data'
2013-05-23 14:14:40 -07:00
Henry Cook
12205b9684
remove obsolete config file reader prototype
2013-05-23 14:09:03 -07:00
Andrew Waterman
fe9adfe71b
Simplify and correct integer multiplier
2013-05-22 17:27:50 -07:00
Yunsup Lee
11133d6d4c
clock gate s2 registers in the frontend
2013-05-21 18:59:21 -07:00
Yunsup Lee
c837c1d800
fix bug in previous JALR commit
...
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
2013-05-21 18:28:44 -07:00
Henry Cook
69b508ff39
ported caches and htif to use new tilelink
2013-05-21 17:21:04 -07:00
Andrew Waterman
28f914c3f2
don't JALR to speculatively-bypassed addresses
...
Technically not necessary, but probably improves performance.
2013-05-21 16:56:58 -07:00
Yunsup Lee
dcde377303
Fix DM I$ deadlock
...
BTB predictions were causing infinite miss loops
2013-05-20 15:22:58 -07:00
Andrew Waterman
3a1b5f01b2
don't take interrupts while they're disabled!
...
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
2013-05-19 23:27:47 -07:00
Andrew Waterman
6eb4c2542a
comment out I$ assert for now
2013-05-18 18:09:23 -07:00
Andrew Waterman
1dab984231
use UFix instead of Bits for arithmetic
2013-05-18 00:45:29 -07:00
Andrew Waterman
dfa7a03f73
use assert, not Assert
2013-05-18 00:45:13 -07:00
Andrew Waterman
d405ffa949
assume all I$ grants bear data
2013-05-01 21:01:20 -07:00
Andrew Waterman
474d321cc7
fix meta hazard counter to reset on new meta writes
2013-05-01 16:35:24 -07:00
Andrew Waterman
a6a88fce19
Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
...
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
2013-05-01 16:34:45 -07:00
Andrew Waterman
63a38e7982
Revert "temp"
...
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
2013-05-01 16:34:33 -07:00
Henry Cook
b6945408cb
temp
2013-05-01 10:24:36 -07:00
Henry Cook
722bc917d3
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
2013-05-01 10:05:54 -07:00
Andrew Waterman
1501e90c1f
interlock probe unit on tag RAW hazards
2013-04-30 00:38:22 -07:00
Henry Cook
e8b20f3d38
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
2013-04-25 17:41:04 -07:00
Andrew Waterman
50ccc20bf3
replace RDNPC with AUIPC
2013-04-22 04:20:15 -07:00
Henry Cook
db5a060c7d
fix io dir
2013-04-10 13:47:30 -07:00
Andrew Waterman
ae7720e284
guarantee LR/SC forward progress
...
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
2013-04-07 19:27:21 -07:00
Andrew Waterman
e74e032c87
simplify MSHR memory response logic
2013-04-06 01:03:37 -07:00
Andrew Waterman
1abb9277db
fix LR/SC atomicity violation
...
note, it's still not starvation-free.
2013-04-05 19:13:38 -07:00
Andrew Waterman
8cbdeb2abf
add LR/SC support
2013-04-04 17:07:09 -07:00
Andrew Waterman
fc46daecf6
don't flush pipeline on writes to side-effect-free PCRs
...
notably, K0, K1, and EPC
2013-04-04 17:07:09 -07:00
Andrew Waterman
8b439ef20d
only support setpcr/clearpcr of SR
...
the full PCR RMW support was wasted area/power
2013-04-04 17:07:08 -07:00
Andrew Waterman
d43f484feb
take interrupts on nonzero fromhost values
2013-04-04 17:07:08 -07:00
Andrew Waterman
d4a3351cfc
expose pending interrupts in status register
2013-04-04 17:07:08 -07:00
Henry Cook
f8aebcbf8c
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
2013-04-04 15:50:29 -07:00
Henry Cook
16113a96ba
fixes after merge
2013-03-25 19:09:08 -07:00
Henry Cook
95f0a688e9
Merge branch 'release-xacts'
...
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
2013-03-20 17:37:50 -07:00
Henry Cook
273bd34091
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
2013-03-20 15:53:36 -07:00
Henry Cook
6d2541aced
nTiles -> nClients in LogicalNetworkConfig
2013-03-20 14:12:36 -07:00
Andrew Waterman
ea9d0b771e
remove aborts; simplify probes
2013-03-19 15:29:40 -07:00
Yunsup Lee
0f50970913
move HellaQueue to uncore
2013-03-19 00:43:20 -07:00
Henry Cook
e0361840bd
writebacks on release network pass asm tests and bmarks
2013-02-28 18:11:40 -08:00
Andrew Waterman
35349d227f
update to new Mem style
2013-02-20 16:09:46 -08:00
Andrew Waterman
9f89c812b7
fix HTIF memory size reporting
2013-01-29 23:08:25 -08:00
Yunsup Lee
a0bd0adeb2
change write/read port ordering for vlsi_mem_gen script
2013-01-29 21:32:42 -08:00
Andrew Waterman
66eb3720a4
fix SRAM semantics bug in HellaFlowQueue
2013-01-29 21:16:42 -08:00
Yunsup Lee
60bd3a6413
Revert "shuffled FPU control logic around to make functional unit retiming work better"
...
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
2013-01-29 19:34:55 -08:00
Andrew Waterman
6275e009f8
fix HellaQueue deq.valid signal
2013-01-28 20:57:43 -08:00
Andrew Waterman
45d8066f45
add HellaQueue, an SRAM-based queue
2013-01-28 20:54:25 -08:00
Andrew Waterman
37c67f1d87
pipeline reset to the vector unit
2013-01-28 17:56:32 -08:00
Rimas Avizienis
f2df6147df
shuffled FPU control logic around to make functional unit retiming work better
2013-01-28 17:17:09 -08:00
Henry Cook
f5729c9f25
removed ack_required field from grant messages
2013-01-28 16:44:17 -08:00
Henry Cook
8cbd316b5e
Merge branch 'ready-sig-fix' into pin-cleanup
2013-01-27 23:04:58 -08:00
Henry Cook
931cffa749
ready signal fix
2013-01-27 23:04:35 -08:00
Henry Cook
83c207c852
pin cleanup in htif
2013-01-27 12:00:28 -08:00
Henry Cook
409b549d3c
actually cleared up tile ios
2013-01-27 11:27:09 -08:00
Henry Cook
696dd102eb
cleans up unconnected tile io pins (networking headers overwritten at top level)
2013-01-27 10:59:41 -08:00
Andrew Waterman
c890099e09
add System Control Register space to HTIF
2013-01-24 23:41:24 -08:00
Andrew Waterman
575bd3445a
re-generalize scoreboard
2013-01-24 18:00:39 -08:00
Andrew Waterman
1fbc20450e
don't allow simultaneous reads and writes to the tag ram
2013-01-24 17:55:00 -08:00
Andrew Waterman
37ee843b2c
don't use reset combinationally
2013-01-24 17:55:00 -08:00
Andrew Waterman
bb6fbddf1f
don't probe the mshr file to inquire about refills
2013-01-24 17:54:59 -08:00
Andrew Waterman
5b9f938263
correctly sign-extend badvaddr, epc, and ebase
2013-01-24 17:54:59 -08:00
Rimas Avizienis
63060bc0a8
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74
New TileLink bundle names
2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d
Refactored packet headers/payloads
2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114
standardize IO naming convention
2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831
Refactored uncore conf
2013-01-07 13:41:36 -08:00
Andrew Waterman
78868f6075
add config option to trade mul/div area for speed
2013-01-06 03:47:17 -08:00
Andrew Waterman
ce9f4881d2
remove broken multiplier early out
2013-01-06 03:47:00 -08:00
Andrew Waterman
05f19b21d0
merge multiplier and divider
2012-12-12 02:22:47 -08:00
Andrew Waterman
c921fc34a9
merge ALU left and right shifters
2012-12-12 02:22:34 -08:00
Andrew Waterman
f5c53ce35d
add ecc support to d$ data rams
...
i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Andrew Waterman
3f59e439ef
fix d$ tag raw hazard
2012-12-07 15:14:20 -08:00
Andrew Waterman
e9752f1d72
pipeline host pcr access
2012-12-06 14:22:07 -08:00
Andrew Waterman
4dda38204f
fix d$ reset bug
2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c
fix AMO and store bypass bugs
...
thanks, torture tester
2012-12-06 02:07:52 -08:00
Andrew Waterman
4608660f6e
torture revealed a couple bugs
...
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
Andrew Waterman
90cae54ac4
fix D$ read/write concurrency bug
2012-11-27 02:42:27 -08:00
Andrew Waterman
9c857b83f0
refactor PCR file
2012-11-27 01:28:06 -08:00
Andrew Waterman
64674d4d39
clean up PTW and support PADDR_BITS < VADDR_BITS
2012-11-26 20:38:45 -08:00
Andrew Waterman
608f65e716
don't wastefully read 2x the bits from D$ RAMs
2012-11-26 20:34:30 -08:00
Andrew Waterman
352bb464b5
clock gate X/M and M/W store data registers
2012-11-26 20:33:41 -08:00
Andrew Waterman
8a6ff5f9aa
fix D$ writeback bug
...
I swear I did this last week... perhaps I am finally losing it!
2012-11-25 19:46:48 -08:00
Andrew Waterman
de2f28193a
get rid of more global constants
2012-11-25 04:24:25 -08:00
Andrew Waterman
c036cdc1ea
add option for 2-cycle load-use delay
2012-11-24 22:01:08 -08:00
Andrew Waterman
b514c7b725
clean up I$ parity code
2012-11-24 22:00:43 -08:00
Andrew Waterman
55082e45c4
add AVec, which automatically infers element type
...
should consider modifying Vec as such
2012-11-24 18:19:28 -08:00
Andrew Waterman
2b26082132
use 1r1w ram for tags; merge tags & permissions
...
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
2012-11-20 04:09:26 -08:00
Andrew Waterman
72f94d1141
fix virtual address sign extension detection
2012-11-20 04:06:57 -08:00
Andrew Waterman
30038bda8a
bypass stores to subsequent loads
...
since we handle subword stores as RMW operations, this occurs frequently
2012-11-20 01:33:32 -08:00
Yunsup Lee
395e4e3dd6
andrew'x fix for D$ corner case in writeback->abort->probe
2012-11-18 03:11:06 -08:00
Yunsup Lee
06eeb90e2a
vector unit interfaces to the new D$
2012-11-17 20:07:41 -08:00
Yunsup Lee
81d711e892
fix D$ bug; now D$ doesn't respond to prefetches
2012-11-17 20:06:13 -08:00
Andrew Waterman
29bc361d6c
remove global constants; disentangle hwacha a bit
2012-11-17 17:24:08 -08:00
Andrew Waterman
5a7777fe4d
clock gate integer datapath more aggressively
2012-11-17 06:48:44 -08:00
Andrew Waterman
cc067026a2
pipeline D$ response -> FPU regfile
2012-11-17 06:48:11 -08:00
Andrew Waterman
e68b039133
fix misc. D$ control bugs
2012-11-17 06:47:27 -08:00
Andrew Waterman
dad7b71062
provide cmd/addr with cache response
2012-11-16 21:26:12 -08:00
Andrew Waterman
cb8ac73045
provide store data with cache response
2012-11-16 21:15:13 -08:00
Andrew Waterman
9e010beffe
fix D$ refill bug
2012-11-16 21:05:29 -08:00
Andrew Waterman
8dce89703a
new D$ with better QoR and AMO pipelining
...
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
a90a1790a5
improve tlb qor
2012-11-16 01:59:38 -08:00
Andrew Waterman
ff8c736d94
move icache invalidate out of request bundle
2012-11-16 01:55:45 -08:00
Andrew Waterman
6d10115b19
fix D$ tag width
2012-11-15 16:46:39 -08:00
Yunsup Lee
be1980dd2d
refactored vector queue interface
2012-11-07 01:15:33 -08:00
Yunsup Lee
8764fe786a
refactored vector tlb
2012-11-06 23:53:52 -08:00
Yunsup Lee
9a02298f6f
andrew's fix for tlb lockup
2012-11-06 23:52:58 -08:00
Andrew Waterman
4d1ca8ba3a
remove more global consts; refactor DTLBs
...
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758
remove more global constants
2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
Yunsup Lee
ee081d1671
modify code to fix UFix := Bits error
2012-11-05 01:35:55 -08:00
Yunsup Lee
2a25307a8f
revamp the vector unit with the new frontend
2012-11-05 01:35:55 -08:00
Andrew Waterman
5b20ed71be
move rd=0 check into bypass logic
...
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
Andrew Waterman
5e103054fd
fix bug in quine mccluskey
2012-11-05 00:28:25 -08:00
Andrew Waterman
e9eca6a95d
refactor I$ config; remove Top class
2012-11-04 16:59:36 -08:00
Andrew Waterman
7380c9fe60
aggressively clock gate int and fp datapaths
2012-11-04 16:40:14 -08:00
Andrew Waterman
bd2d61de03
use 8T SRAM for I$; gate clock more aggressively
2012-11-04 16:39:25 -08:00
Andrew Waterman
fedee6c67d
add generic error correcting codes
2012-10-30 01:03:47 -07:00
Andrew Waterman
5773cbb68a
rejigger htif to use UncoreConfiguration
2012-10-18 17:26:03 -07:00
Henry Cook
e2eb7ce8e9
Cleanup git incompetence
2012-10-16 16:54:58 -07:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Henry Cook
6cff1c13d8
Refer to traits moved to uncore, add UncoreConfiguration to top
2012-10-16 14:22:23 -07:00
Andrew Waterman
b9a2af697d
turn off HAVE_VEC as it's currently broken
...
the new I$/frontend needs to be integrated
2012-10-16 07:38:19 -07:00
Andrew Waterman
0a640f2cc6
make DecodeLogic deterministic (hopefully)
2012-10-16 04:51:21 -07:00
Andrew Waterman
5821900329
don't refetch from I$ if on same 16B block
2012-10-16 02:24:38 -07:00
Andrew Waterman
b955985b38
improve divider QoR
2012-10-16 02:24:38 -07:00
Andrew Waterman
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
Andrew Waterman
fc648d13a1
remove old Mux1H; add implicit conversions
2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Andrew Waterman
fcd69dba98
add optional early-out to mul/div
2012-10-16 02:24:37 -07:00
Andrew Waterman
27ddff1adb
simplify and improve multiplier
2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2
improvements to implicit RocketConfiguration parameter
2012-10-15 16:29:49 -07:00
Henry Cook
a7a4e65690
Initial verison of reading config from files
2012-10-15 16:05:50 -07:00
Henry Cook
5d2a470215
all rocket-specific arbiters in one file and refactored traits slightly
2012-10-15 16:05:32 -07:00
Huy Vo
1864e41361
memserdes + slowio out of rocket and into uncore
2012-10-10 15:25:24 -07:00
Huy Vo
fe21142972
fixed memdessert unpacking
2012-10-09 13:03:17 -07:00
Henry Cook
9025d0610c
first pass at configuration object passed as implicit parameter
2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092
decode constant object split into multiple objects
2012-10-05 15:50:42 -07:00
Andrew Waterman
ed8cc4a1cf
eliminate D$ probe->WB critical path
2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37
factoring out uncore into separate uncore repo
2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5
uncore and rocket changes for new xact types
2012-10-01 10:47:36 -07:00
Huy Vo
d9cb96c0ae
factored out common stuff to ChiselUtil
2012-09-27 22:53:34 -07:00
Andrew Waterman
667b4ee858
remove Queue flush port (override reset instead)
2012-08-22 13:39:19 -07:00
Andrew Waterman
d4a001b867
add PriorityMux; use to implement PriorityEncoder
2012-08-22 13:38:25 -07:00
Andrew Waterman
743e032f06
generalize interface to DecodeLogic
2012-08-22 13:38:07 -07:00
Andrew Waterman
0f20771664
rename queue to Queue
...
fixes build with case-insensitive file system
2012-08-08 22:11:59 -07:00
Andrew Waterman
897a4e349b
fix some LLC control bugs
2012-08-06 17:10:04 -07:00
Andrew Waterman
e9c35b4923
ameliorate DTLB kill->rdy critical path
2012-08-06 17:05:05 -07:00
Andrew Waterman
b94e6915ab
refactor IPIs; use new tohost/fromhost protocol
2012-08-03 19:00:34 -07:00
Andrew Waterman
6510f020c7
fix deadlock in coherence hub
2012-08-03 19:00:03 -07:00
Andrew Waterman
e3726c4db0
fix control bug in LLC
...
structural hazard on tag ram caused deadlock
2012-08-03 18:59:37 -07:00
Andrew Waterman
def913096e
pipeline LLC further
2012-07-31 17:45:14 -07:00
Andrew Waterman
3a8f3e0de5
further pipeline the LLC
2012-07-30 20:12:11 -07:00
Andrew Waterman
80c243469e
add flow queues and skid buffers
...
hopefully they work
2012-07-30 18:47:12 -07:00
Andrew Waterman
be4fa936dd
fix PriorityEncoderOH bug
2012-07-30 18:28:54 -07:00
Andrew Waterman
2ec76390e3
improve PriorityEncoderOH and add Counter util
2012-07-30 16:06:55 -07:00
Yunsup Lee
2af84f994a
remove reset pin on llc
2012-07-28 21:14:51 -07:00
Yunsup Lee
0a1cd1175c
add reset pin to llc
2012-07-27 18:44:39 -07:00
Huy Vo
db91c4cf6c
hwacha
2012-07-27 18:13:20 -07:00
Huy Vo
32a16d183f
consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false
2012-07-27 18:13:20 -07:00
Andrew Waterman
130fa95ed6
expand HTIF's PCR register space
2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395
reduce number of outstanding transactions
2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19
remove chip-specific uncore gunk
2012-07-26 03:26:52 -07:00
Andrew Waterman
a5bea4364f
memory system bug fixes
2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf
change htif width to 16
2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9
merge HTIF port and backup memory port
2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07
change llc size
2012-07-24 14:10:29 -07:00
Yunsup Lee
6541cf22a4
fix bug in coherence hub, respect xact_rep.ready
2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1
hoist HTIF_WIDTH out to consts
2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114
fix htif split request/response
2012-07-23 17:15:16 -07:00
Andrew Waterman
938effc053
don't dequeue probe queue during reset
2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359
change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1
hoist out uncore as its own component
2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d
type casting
2012-07-18 13:03:35 -07:00
Andrew Waterman
f42c6afed2
decouple all interfaces between tile and top
...
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722
fix dcache tag array size
2012-07-16 22:19:03 -07:00
Andrew Waterman
e496cd7584
use Mem to implement queues to speed things up
2012-07-13 21:48:05 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3
use only one (wide) tag ram for set assoc. caches
2012-07-12 14:50:12 -07:00
Andrew Waterman
429fcbed8e
fix some LLC bugs
2012-07-11 17:56:39 -07:00
Andrew Waterman
f645fb4dd7
add L2$
...
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36
update to new chisel
2012-07-08 17:59:41 -07:00
Andrew Waterman
39d198ecdc
fix htif handling of large memory reads
2012-06-26 19:12:11 -07:00
Andrew Waterman
4e5f874266
update to new chisel/hwacha
2012-06-08 00:13:14 -07:00
Huy Vo
a99cebb483
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788
moving util out into Chisel standard library
2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Andrew Waterman
943b6d0616
remove debug println
2012-06-06 02:48:48 -07:00
Andrew Waterman
7f6319047e
update to new scala/chisel/Mem
2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Huy Vo
181b20d69c
working vec unit with pvfb
2012-05-24 10:38:14 -07:00
Andrew Waterman
faee45bf4c
fix setpcr/clearpcr not writing rd
2012-05-21 07:25:35 -07:00
Yunsup Lee
c9602a0d2e
fix vector control decode bug
2012-05-15 10:26:37 -07:00
Gage W Eads
d0bc995c88
Fixed IRQ_IPI -> IRQ_TIMER typo
2012-05-14 22:25:12 -07:00
Andrew Waterman
a2f6d01c1b
add programmable coreid register
2012-05-09 03:09:22 -07:00
Andrew Waterman
e0e1cd5d32
add IPIs and an IPI test
...
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
2012-05-08 22:58:00 -07:00
Henry Cook
87cbae2c8a
Removed defunct ioDmem
2012-05-07 17:31:39 -07:00
Andrew Waterman
b851f1b34c
support maximum-MTU HTIF packets
2012-05-03 21:11:43 -07:00
Andrew Waterman
171c87002e
reduce HTIF clock divider for now
2012-05-03 04:21:11 -07:00
Andrew Waterman
e1f9dc2c1f
generalize page table walker
...
also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 02:29:09 -07:00
Andrew Waterman
2d4e5d3813
fix pseudo-LRU verilog generation bug
2012-05-02 19:31:31 -07:00
Henry Cook
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122
improved instruction decoding
...
it now makes use of don't-cares by performing logic minimization
2012-05-01 20:16:36 -07:00
Andrew Waterman
4cfa6cd9a8
force Top.main's return type to Unit
2012-05-01 19:55:16 -07:00
Andrew Waterman
5819beed64
use parameterized FP units
2012-05-01 01:25:43 -07:00
Andrew Waterman
eafdffe125
simplify page table walker; speed up emulator
2012-05-01 01:24:36 -07:00
Andrew Waterman
c13d3e6f88
fix probe tag read-modify-write atomicity violation
2012-04-26 02:29:31 -07:00
Andrew Waterman
66f86a2194
use pseudo-LRU replacement for TLBs
2012-04-26 02:29:30 -07:00
Andrew Waterman
a0378c5d2f
remove faulting TLB entry after page fault
...
this vastly reduces the frequency with which the TLB must be flushed
2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378
fix DTLB permissions bug
2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4
Fixed coherence bug: probe counting for single tile
2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1
Fixed abort bug: xact_abort.ready was not pinned high
2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150
fix AMO replay/coherence deadlock
2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f
fix writeback bug
2012-04-13 03:16:48 -07:00