cddfdf0929
Add CHISEL_VERSION make argument
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This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
d697559754
Correct the polarity of the non-backup-memory HTIF
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This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
7d5eac189b
Bump the uncore for some Chisel3 fixes
2016-03-24 12:00:13 -07:00
4744deec28
Fix the SCR file for Chisel 3
2016-03-24 12:00:13 -07:00
476db6ef39
Move to a newer Scala version
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Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
c6e974b110
Merge pull request #30 from ucb-bar/chisel3
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Chisel 3 support
2016-03-24 11:52:02 -07:00
471f4c2695
change WriteMaskedPutBlockRegression for better bug detection
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Instead of sending puts back-to-back, separate the two puts with a get.
Also, stall a bit between each transaction. This makes sure the puts and
intermediate get are sent to the same transactor, which will cause the
data buffer to get overwritten between the two puts.
2016-03-23 16:31:19 -07:00
c9e1b72972
Don't assign SInt(-1) to a UInt
2016-03-23 16:24:27 -07:00
3b0e87f42a
pass CSRs through to ground test and get DMA tests working again
2016-03-22 20:18:02 -07:00
7b7e954133
make sure DummyPTW does not invalidate the TLB
2016-03-22 19:59:58 -07:00
6da45e7f26
Trace generator: updates and additions to the scripts directory.
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(1) Introduce tracegen.py, a script that invokes the emulator (built
with TraceGenConfig), sending a SIGTERM once all cores are finished.
(2) Update toaxe.py to gather some statistics about the trace.
(3) Introduce tracestats.py, which displays the stats in a useful way.
(4) Introduce tracegen+check.py, a top-level script that generates
traces, checks them, and emits stats. If this commit is pulled, it
should be done after pulling my latest groundtest commit.
2016-03-21 15:28:15 -07:00
aa22f175c3
Add cloneType methods for Chisel3
2016-03-21 13:35:02 -07:00
c989ec5813
Fix the SCR file for Chisel 3
2016-03-21 11:55:40 -07:00
1344d09cef
Fix the SCR file for Chisel 3
2016-03-21 11:55:18 -07:00
bda5772e98
Updates to the trace-generator: (1) Don't terminate via HTIF exit, which can cause other, unfinished, cores to be cut short. Instead emit FINISHED messsages allowing an external process to send a SIGTERM to the emulator once all cores have finished. (2) Add some support for greater address variation without having to recompile, disabled by default. (3) Generate atomic, LR/SC, and fence operations by default in addition to plain loads and stores. These changes require newer versions of files in the rocket-chip/scripts directory. I will submit a pull request for those too.
2016-03-18 12:11:11 +00:00
c13b8d243d
BroadcastHub race on allocating VolWBs vs Acquires
2016-03-17 18:32:35 -07:00
5f3d3a0b2d
Bugfix for probe flags in L2BroadcastHub
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Closes #25
2016-03-17 16:42:40 -07:00
49d82864bf
Fix StoreDataQueue allocation bug in BroadcastHub
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Closes #27
2016-03-17 12:31:18 -07:00
b5992186df
include top-level makefrag in regressions
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fixes issue with rocketchip_addons inclusion
2016-03-16 15:52:28 -07:00
e90a9dfb2b
make taking max of multiple integers in config a bit easier
2016-03-16 14:35:08 -07:00
4fc2a14a63
Fix MIF bug that cuts off upper xact id bits
2016-03-16 13:50:30 -07:00
8a47c3f346
Make sure there's enough xact id bits
2016-03-16 13:49:30 -07:00
04be438847
Avoid conflicting assigments to registers in timers. Give priority to start over stop.
2016-03-16 12:54:19 -07:00
137b77d780
Merge pull request #4 from ucb-bar/chisel3
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Work around Chisel3's lack of 0-width wires
2016-03-15 17:30:34 -07:00
50f61687de
Work around Chisel3's lack of 0-width wires
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This is super ugly, but it's necessary to get Chisel3 to compile. Note
that this still fails simulations in Chisel3, so it might be wrong.
2016-03-14 22:50:37 -07:00
9dc0cbdfa4
WIP on privileged spec v1.9
2016-03-14 18:03:33 -07:00
13dcb96b7f
Update TLB interface
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n.b. no need to set mprv, since prv = S.
2016-03-14 17:55:19 -07:00
648437e7cb
Merge pull request #70 from ucb-bar/add-rv32-support
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Add RV32 test/configuration options
2016-03-14 17:06:39 -07:00
db09f310a1
Define MIFMasterTagBits as # bits a master can *use* in tag
2016-03-11 16:48:13 -08:00
f2ded2721d
Merge branch 'master' into add-rv32-support
2016-03-10 19:33:04 -08:00
25091003af
Add RV32 test/configuration options
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These won't actually work until further commits. Rocket RV32 support
is complete, but on the priv-1.9 branch.
2016-03-10 17:40:21 -08:00
67e711844a
index extraction bug
2016-03-10 17:37:40 -08:00
e2185d40f6
Avoid right-shift by larger that the bit width
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FIRRTL bails out on this. There's an outstanding bug, this is just a
workaround. See https://github.com/ucb-bar/firrtl/issues/69
2016-03-10 17:37:40 -08:00
8c7e29eacd
Avoid generating 0-width UInts
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Chisel3 requires a 1-bit width to represent UInt(0).
2016-03-10 17:37:40 -08:00
2eafc4c8f3
Extend AMOALU to support RV32
2016-03-10 17:32:23 -08:00
c28d115b30
Chisel3 compatibility fix
2016-03-10 17:32:23 -08:00
7ae44d4905
Add RV32 support
2016-03-10 17:32:00 -08:00
82c595d11a
Fix no-FPU elaboration of CSR file
2016-03-10 17:30:56 -08:00
93773a4496
Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
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To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).
Closes #18
Closes #20
2016-03-10 17:14:34 -08:00
67ad36d74a
Merge pull request #69 from ucb-bar/fix-tabs
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tabs are evil
2016-03-10 16:17:46 -08:00
7a75a03123
tabs are evil
2016-03-10 14:18:56 -08:00
3c9e63f5a5
don't make HTIF clock divider tied to backup memory
2016-03-09 14:58:20 -08:00
3e721fe80b
Merge pull request #2 from ucb-bar/chisel3
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Pass a BitPat to Lookup
2016-03-06 04:27:52 -08:00
bf06ba0d37
Pass a BitPat to Lookup
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This is the only supported type of Lookup in Chisel 3.
2016-03-05 18:50:56 -08:00
36f2e6504c
Fix width of NastiROM rows, preventing out-of-range extraction
2016-03-03 16:57:16 -08:00
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
5e145515e1
fix some Chisel assertions
2016-03-02 14:50:49 -08:00
7eef3393f1
fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant
2016-03-02 14:11:45 -08:00
57370bdf49
first and last on HasTileLinkData
2016-03-02 14:11:39 -08:00
9c7e5bc6c0
bump hardfloat, tools(tests & spike) for fcvt fix
2016-03-01 19:53:26 -08:00
