Andrew Waterman
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
Matthew Naylor
213bb26367
Drive invalidate_lr signal
...
The DCache input for invalidating LR reservations was dangling. Now
we wire it to false.
2016-05-25 13:27:12 +01:00
Donggyu
a9599302bd
fix cloneType in nasti.scala ( #14 )
2016-05-24 17:10:17 -07:00
Andrew Waterman
5bc78aba99
Merge pull request #15 from terpstra/ahb
...
Ahb
2016-05-24 17:06:03 -07:00
Andrew Waterman
c49cb10c74
Merge pull request #42 from terpstra/ahb
...
Ahb
2016-05-24 17:02:15 -07:00
Andrew Waterman
4605b616c1
Fix bug in D$ AMO/storegen logic
2016-05-24 16:26:07 -07:00
Andrew Waterman
88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
Andrew Waterman
5dac7b818d
Support set associativity in blocking D$
2016-05-24 15:45:52 -07:00
Andrew Waterman
e0addb5723
Support uncached AMOs in blocking D$
2016-05-24 15:45:35 -07:00
Andrew Waterman
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
Andrew Waterman
3b35c7470e
Add uncached support to blocking D$
2016-05-24 15:05:41 -07:00
Andrew Waterman
42f079ce57
JAL requires DW_XPR
...
This has been benign so far because of how the logic minimization worked.
2016-05-24 15:05:41 -07:00
Andrew Waterman
b92c73e361
Add LR/SC to blocking D$
2016-05-24 15:05:41 -07:00
Andrew Waterman
0d93d1a1a0
Clean up pending store logic a bit
2016-05-24 15:05:41 -07:00
Andrew Waterman
0b8de578d4
Add additional D$ store buffering to prevent structural hazards
2016-05-24 15:05:41 -07:00
Andrew Waterman
354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
...
This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
Andrew Waterman
d7790ac6a4
WIP on blocking D$
2016-05-24 15:05:41 -07:00
Andrew Waterman
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
Andrew Waterman
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
Andrew Waterman
a3061047e3
Instantiate blocking D$ when NMSHRS=0
2016-05-24 15:05:41 -07:00
Andrew Waterman
80482890fd
Don't rely on tag value for nacks
2016-05-24 15:05:41 -07:00
Wesley W. Terpstra
e19c5e5d2c
IOMSHR: support atomic operations
2016-05-24 15:00:50 -07:00
Wesley W. Terpstra
a012341d96
ahb: TileLink => AHB bridge, including atomics and bursts
2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
ace9362d81
ahb: amoalu does not need so many parameters! (i want to reuse it)
2016-05-24 14:58:27 -07:00
Wesley W. Terpstra
b921bae107
ahb: eliminate trait abused for constants
2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
200c69c106
ahb: support hmastlock acquistion of crossbar
2016-05-24 14:20:45 -07:00
Wesley W. Terpstra
e1e8eda419
ahb: add a test SRAM
2016-05-24 14:20:42 -07:00
Wesley W. Terpstra
1db40687c6
ahb: eliminate now-unnecesary non-standard hreadyin
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
15cad8414d
ahb: put signals in the order they appear in signal traces in the spec
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
f30f8d9f79
ahb: reduce obsolete degenerate cases of a crossbar
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
0368b6db6b
ahb: replace defective crossbar with a functional one
...
The previous crossbar had the following bugs:
1. a bursting master could be preempted
the AHB-lite spec requires a slave receive the entire burst
2. a waited master could be replaced
the AHB-lite spec requires haddr/etc to remain unchanged
3. hmastlock did no ensure exclusive access
atomic operations could be pre-empted
2016-05-24 14:14:22 -07:00
Wesley W. Terpstra
2b37f37335
ahb: helper methods
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
ef2aae26a8
ahb: rename hreadyout to standard hready, mark hreadyin for death
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
2f8a77f27a
ahb: include all AHB-lite constants
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
7896c4157e
ahb: parameterize poci
2016-05-24 14:14:21 -07:00
Wesley W. Terpstra
93447eb274
ahb: make hasti parameters location sensitive
2016-05-24 14:14:17 -07:00
Wesley W. Terpstra
00d31dc5c5
bram: use new hasti definitions
2016-05-24 13:35:16 -07:00
Albert Ou
ee0acc1d07
Fix BRAM assertion condition
2016-05-23 13:19:53 -07:00
Matthew Naylor
05c0808ff2
Update trace generation and checking scripts
...
Pass the elf file (that specifies the tohost and fromhost addresses)
to the emulator in the trace generator & checker scripts.
2016-05-23 17:02:15 +01:00
Andrew Waterman
7bc38383de
add (non-working) blocking data cache
2016-05-20 18:59:05 -07:00
Colin Schmidt
3e0b5d6fd9
Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,
...
but would otherwise be allocated.
Closes #45
2016-05-20 16:35:30 -07:00
Ken McMillan
fd83d20857
Use a def instead of a lazy val in ManagerCoherenceAgent.
...
Prevents C++ emulator from randomizing inputs in unit testing.
Closes #44
2016-05-20 16:31:12 -07:00
Howard Mao
f228309bd1
add assertion to make sure SimpleHellaCacheIF doesn't get exception
2016-05-20 16:30:27 -07:00
Ken McMillan
d69446e177
Add config classes to drive unit testing of L2 TileLink agents.
...
Closes #43
2016-05-20 16:15:43 -07:00
Howard Mao
87be2bcd60
make sure TraceGen addresses are correct
2016-05-20 16:12:11 -07:00
Howard Mao
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
Howard Mao
4f84d8f757
make sure to hook up finish in ClientTileLinkEnqueuer
2016-05-18 13:13:34 -07:00
Colin Schmidt
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
Colin Schmidt
b396c68577
bump torture for priv-1.9 test-env
2016-05-17 22:02:38 -07:00
