riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo 2016-07-28 11:27:29 -07:00
Howard Mao ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo 2016-07-28 11:23:31 -07:00
Howard Mao aefba04fb3 get rid of submodules in preparation for merging 2016-07-28 11:21:08 -07:00
Howard Mao 6de2a3e3b1 get rid of fpga-zynq submodule 2016-07-28 11:07:47 -07:00
Howard Mao fe51a35fa9 a few more submodule bumps 2016-07-28 09:25:59 -07:00
Howard Mao bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao fbcc7317cf make sure PseudoLRU is given power of 2 ways 2016-07-27 18:39:33 -07:00
Howard Mao 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao 9c89290efc fix LRSC issue (fixes issue #86) 2016-07-26 22:25:04 -07:00
Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86) 
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
 2016-07-26 18:41:52 -07:00
Howard Mao ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue 
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
 2016-07-26 12:31:08 -07:00
Howard Mao 1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Howard Mao 51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Howard Mao 75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge 
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
 2016-07-21 19:41:56 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Howard Mao 0a1cd64786 fix number of builtin Acquire types 2016-07-21 13:45:20 -07:00
Howard Mao ffe17cbb2b bump uncore for L2 bugfix 2016-07-21 12:35:38 -07:00
Howard Mao 20df74d138 generate more L1 voluntary releases in TraceGen 2016-07-21 12:33:55 -07:00
Howard Mao 86e31be820 fix lockup from back to back releases with data 2016-07-21 12:06:58 -07:00
Howard Mao 19b44ec95b Bug fixes in SimpleHellaCacheIF and L2 agents 
* SimpleHellaCacheIF now properly handles both the non-blocking data
   cache and blocking data cache.
 * SimpleHellaCacheIF maintains ordering of replayed requests
 * L2 VoluntaryReleaseTracker sends voluntary release grant properly
 * Coherence protocols now downgrade for probeCopy
 2016-07-19 09:35:13 -07:00
Howard Mao 9eeb1112d4 fix Bufferless irel_vs_iacq_conflict signal 2016-07-18 17:38:20 -07:00
Howard Mao e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao 2723b2f515 fix issues in SimpleHellaCacheIF and document the changes 2016-07-18 17:02:47 -07:00
Howard Mao 40a146f625 HellaCacheArbiter passes through if n == 1 2016-07-18 17:01:29 -07:00
Howard Mao 39a1ecbf3c switch groundtest to merged master 2016-07-18 09:34:27 -07:00
Howard Mao e08ec42bc0 refactor groundtest unittests into separate package 2016-07-16 23:19:55 -07:00
Howard Mao 84098db81f add a TileLinkTestRAM 2016-07-15 11:03:26 -07:00
Howard Mao 18ea58c85f remove unnecessary CAMs from converters 2016-07-13 12:42:50 -07:00
Howard Mao b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao 4c79215fde add a script for checking comparator trace 2016-07-12 14:42:04 -07:00
Howard Mao 90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao 8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao b64998ec05 make sure dramsim reads and writes occur in the order they are received 2016-07-11 18:11:00 -07:00
Howard Mao cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Howard Mao 9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao 35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao 358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Howard Mao 8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Howard Mao f7b392306e make sure SimpleHellaCacheIF can work with blocking DCache 2016-07-07 18:59:23 -07:00
Howard Mao 16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao 7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao 1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao 8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao 8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao 5d8d5e598b add buffering and locking to TL -> Nasti converter 2016-07-06 16:51:45 -07:00
Howard Mao b10d306b4a add option to log L2 cache transactions for easier debugging 2016-07-06 14:59:09 -07:00
Howard Mao 64afc795fd make sure voluntary releases don't get allocated to L2WritebackUnit 2016-07-06 14:10:45 -07:00
Howard Mao f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao b105076996 fix ID mapper to disallow two in-flight requests with the same inner ID 2016-07-05 17:41:46 -07:00
Howard Mao af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Howard Mao c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao 702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00
Howard Mao 06ed9c5794 add a single-entry queue in front of acquire and release for bufferless broadcast hub 2016-07-05 12:08:22 -07:00
Howard Mao 67bac383e3 hopefully fixed last bugs in Bufferless 2016-07-05 12:08:22 -07:00
Howard Mao a35388bc27 fix merging of same xact ID puts/gets 2016-07-05 12:08:22 -07:00
Howard Mao 51f7bf1511 fix Bufferless voluntary release issue 2016-07-05 12:08:22 -07:00
Howard Mao afc51c4a35 make sure TL -> NASTI converter handles multibeat transactions properly 2016-07-05 12:08:22 -07:00
Howard Mao af51b6f363 bump groundtest and uncore 2016-07-01 18:13:46 -07:00
Howard Mao b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao caa9ca24b9 NASTI -> TL converter also uses ID mapper 2016-07-01 18:11:29 -07:00
Howard Mao e163a23583 fix another bug in Widener 2016-07-01 16:24:48 -07:00
Howard Mao 10a46a36ae fix full_addr() function in TileLink 2016-07-01 15:17:41 -07:00
Howard Mao e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao 61e3e5b45a more WIP on fixing Bufferless 2016-06-30 18:29:51 -07:00
Howard Mao 0eedffa82f WIP: Fix BufferlessBroadcastHub 2016-06-30 18:29:51 -07:00
Howard Mao 600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao ce46f523c9 make sure Widener uses proper parameters to generate acquire/grant 2016-06-30 18:17:16 -07:00
Howard Mao a0b1772404 change TileLinkWidthAdapter interface 2016-06-30 15:50:23 -07:00
Howard Mao 39ec927a3f replace complicated pattern substitutions with automatic variable 2016-06-28 18:30:11 -07:00
Howard Mao a39a0c0ec4 .prm is output of chisel stage, not firrtl stage 2016-06-28 17:34:37 -07:00
Howard Mao b30e0254ee fix Makefrag to detect all Chisel source files 2016-06-28 16:39:10 -07:00
Howard Mao ebef4ddad0 remove mention of HTIF from README 2016-06-28 15:23:32 -07:00
Howard Mao 74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Howard Mao a9e0a5e2df changes to imports after uncore refactor 2016-06-28 14:09:31 -07:00
Howard Mao 9feca99d5d make PutBlock wmask argument match Put 2016-06-28 13:10:46 -07:00
Howard Mao b936aa9826 refactor uncore files into separate packages 2016-06-28 13:10:46 -07:00
Howard Mao d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao ec5b9dfc86 make sure trackers can handle case where there are no caching clients 2016-06-27 16:29:51 -07:00
Howard Mao 2dd8d90ae4 make Comparator fit the GroundTest model 2016-06-27 16:01:32 -07:00
Howard Mao a93a70c8ec make sure merged voluntary releases are handled properly 2016-06-27 11:40:32 -07:00
Howard Mao 800e62412a use the fast version of asm/bmark-tests 2016-06-24 15:36:10 -07:00
Howard Mao d6ba0437ff merge different configs into regression suites to reduce travis build times 2016-06-24 13:02:29 -07:00
Howard Mao 4cd709c516 fix Comparator in groundtest 2016-06-23 15:47:24 -07:00
Howard Mao 255ef05e21 bump rocket 2016-06-22 17:59:05 -07:00
Howard Mao 338f959620 get rid of commented out code 2016-06-22 17:36:53 -07:00
Howard Mao 4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao 4c31248917 make sure UseAtomics is on when PTW is being used 2016-06-22 16:09:45 -07:00
Howard Mao 5edb448a1f get rid of slow DualCoreConfig in Travis for now 2016-06-22 16:09:14 -07:00
Howard Mao 3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao 9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00