 Huy Vo
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09247c0e0b
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fix to sram init pins
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2013-09-19 20:12:10 -07:00 |
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Huy Vo
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c9813603ee
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Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2
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2013-09-19 20:11:11 -07:00 |
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Huy Vo
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cc3dc1bd0f
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bug fix
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2013-09-19 20:10:56 -07:00 |
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Huy Vo
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d7d13255db
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chisel tag
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2013-08-12 20:53:29 -07:00 |
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Huy Vo
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f9d1403a92
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tags
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2013-08-12 20:53:17 -07:00 |
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Huy Vo
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cc6631ae4d
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reset -> _reset
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2013-08-12 20:52:55 -07:00 |
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Huy Vo
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d5c9eb0f54
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reset -> resetVal, getReset -> reset
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2013-08-12 20:52:18 -07:00 |
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Huy Vo
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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Huy Vo
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2ac3fd5306
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get rid of init_node
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2013-04-20 01:36:32 -07:00 |
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Huy Vo
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0d87e3bacc
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fixed init pin generation
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2013-04-20 00:38:01 -07:00 |
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Huy Vo
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f67f8829e3
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new rocket + uncore tags, added uncore dependencies to Makefrag
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2012-10-10 15:44:19 -07:00 |
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Huy Vo
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08ab076217
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forgot to change package + using fromBits in memserdes instead of manual unpacking
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2012-10-10 15:42:39 -07:00 |
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Huy Vo
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1864e41361
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memserdes + slowio out of rocket and into uncore
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2012-10-10 15:25:24 -07:00 |
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Huy Vo
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9610622ab0
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moving memserdes + slowio into src
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2012-10-10 12:41:11 -07:00 |
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Huy Vo
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35f213e735
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Merge branch 'master' of ../rocket-clone
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2012-10-10 12:39:48 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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Huy Vo
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fe21142972
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fixed memdessert unpacking
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2012-10-09 13:03:17 -07:00 |
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Huy Vo
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916c1019af
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fixed memdessert unpacking
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2012-10-09 13:03:17 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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Huy Vo
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8560ea6e40
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rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
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2012-10-01 19:12:18 -07:00 |
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Huy Vo
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cf8f20584e
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Huy Vo
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e909093f37
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Huy Vo
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2413763f3d
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henry's uncore and rocket changes for new xact types
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2012-10-01 16:05:37 -07:00 |
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Huy Vo
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d9cb96c0ae
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factored out common stuff to ChiselUtil
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2012-09-27 22:53:34 -07:00 |
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Huy Vo
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fa8075570a
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move srcs into src dir, factoring out uncore consts into consts
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2012-09-27 12:59:45 -07:00 |
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Huy Vo
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084a0d31c3
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initial commit, all the relevant submodules
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2012-09-26 17:46:17 -07:00 |
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Huy Vo
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db91c4cf6c
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hwacha
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2012-07-27 18:13:20 -07:00 |
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Huy Vo
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32a16d183f
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consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false
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2012-07-27 18:13:20 -07:00 |
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Huy Vo
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0a97d6ab4d
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type casting
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2012-07-18 13:03:35 -07:00 |
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Huy Vo
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a79747a062
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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18bc14058b
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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Huy Vo
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166b857055
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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0c6bade592
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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a99cebb483
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
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Huy Vo
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9b3161920f
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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f2942f79f9
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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c975c21e44
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views removed
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2012-06-06 12:51:26 -07:00 |
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Huy Vo
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6f2f1ba21c
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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0208e9f95e
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Huy Vo
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181b20d69c
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working vec unit with pvfb
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2012-05-24 10:38:14 -07:00 |
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Huy Vo
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c9c3bd02bc
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kill mem stage if fpu nacks in mem stage
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2012-04-01 17:02:32 -07:00 |
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Huy Vo
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c7c35322c2
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two bug fixes to fpu
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2012-03-31 22:23:51 -07:00 |
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Huy Vo
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1b733e7cf0
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
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Huy Vo
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6e32cc8b20
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
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Huy Vo
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fdffb124e3
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-03-13 12:34:39 -07:00 |
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Huy Vo
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6fd1527476
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fix to rocket vec_dpath, updating makefiles to run xcpt test cases
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2012-03-13 12:34:02 -07:00 |
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Huy Vo
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0fd777f480
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
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Huy Vo
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aa099a53fa
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
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Huy Vo
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93f41d3359
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
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Huy Vo
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e22106af3f
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updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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2012-02-26 17:24:08 -08:00 |
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Huy Vo
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5b0f7ccf68
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updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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2012-02-26 17:24:08 -08:00 |
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