Merge branch 'master' of github.com:ucb-bar/riscv-rocket
This commit is contained in:
Huy Vo
commit
fdffb124e3
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@ -147,8 +147,8 @@ trait FourStateCoherence extends CoherencePolicy {
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
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(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
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}
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//TODO: do we need isPresent() for determining that a line needs to be
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@ -600,7 +600,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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conflicts(i) := t.busy && x_init.valid && coherenceConflict(t.addr, x_init.bits.address)
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}
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x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
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want_to_abort_arr(j) := conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits))
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want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits)))
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x_abort.valid := Bool(false)
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switch(abort_state_arr(j)) {
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@ -94,7 +94,7 @@ class LoadDataGen extends Component {
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class MSHRReq extends Bundle {
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val tag_miss = Bool()
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val old_state = UFix(width = 2)
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val old_dirty = Bool()
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val old_tag = Bits(width = TAG_BITS)
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val tag = Bits(width = TAG_BITS)
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@ -252,7 +252,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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req := io.req_bits
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when (io.req_bits.tag_miss) {
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state := Mux(needsWriteback(io.req_bits.old_state), s_wb_req, s_refill_req)
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state := Mux(io.req_bits.old_dirty, s_wb_req, s_refill_req)
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}
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}
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@ -722,8 +722,8 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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// reset and flush unit
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val flusher = new FlushUnit(lines)
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val flushed = Reg(resetVal = Bool(true))
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flushed := flushed && (!r_cpu_req_val_ || r_req_flush) || r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val_ && r_req_flush && mshr.io.fence_rdy && !flushed
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flushed := flushed && (!r_cpu_req_val || r_req_flush) || r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && !flushed
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flusher.io.mshr_req.ready := mshr.io.req.ready
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when (io.cpu.req_val) {
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@ -774,13 +774,13 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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meta_arb.io.in(2).bits.way_en := ~UFix(0, NWAYS)
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val early_tag_nack = !meta_arb.io.in(2).ready
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val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
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val tag_match_arr = (0 until NWAYS).map( w => isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_match_arr = (0 until NWAYS).map( w => isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
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val tag_hit = r_cpu_req_val && tag_match
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val tag_miss = r_cpu_req_val && !tag_match
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val hit_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
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val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), hit_way_oh, meta.io.way_en)
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val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), hit_way_oh, data.io.way_en)
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val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
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val tag_hit_arr = (0 until NWAYS).map( w => isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
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val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
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val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
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val meta_resp_mux = Mux1H(meta_resp_way_oh, meta.io.resp)
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val data_resp_mux = Mux1H(data_resp_way_oh, data.io.resp)
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@ -809,8 +809,6 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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data_arb.io.in(4).bits.inner_req.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
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data_arb.io.in(4).bits.inner_req.idx := io.cpu.req_idx(indexmsb,indexlsb)
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data_arb.io.in(4).bits.inner_req.rw := Bool(false)
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data_arb.io.in(4).bits.inner_req.wmask := UFix(0) // don't care
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data_arb.io.in(4).bits.inner_req.data := io.mem.xact_rep.bits.data // don't care
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data_arb.io.in(4).valid := io.cpu.req_val && req_read
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data_arb.io.in(4).bits.way_en := ~UFix(0, NWAYS) // intiate load on all ways, mux after tag check
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val early_load_nack = req_read && !data_arb.io.in(4).ready
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@ -831,16 +829,16 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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val drain_store = drain_store_val && data_arb.io.in(2).ready
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val p_amo = Reg(resetVal = Bool(false))
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val p_store_rdy = !(p_store_valid && !drain_store) && !(mshr.io.data_req.valid || r_replay_amo || p_amo)
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p_amo := tag_hit && r_req_amo && mshr.io.req.ready && !nack_hit || r_replay_amo
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p_store_valid := p_store_valid && !drain_store || (tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
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p_amo := r_cpu_req_val && tag_hit && r_req_amo && mshr.io.req.ready && !nack_hit || r_replay_amo
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p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
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// tag update after a store to an exclusive clean line.
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val new_hit_state = newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
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val set_hit_state = tag_hit && meta_resp_mux.state != new_hit_state
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val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
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meta.io.state_req.bits.inner_req.rw := Bool(true)
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meta.io.state_req.bits.inner_req.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
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meta.io.state_req.bits.inner_req.data.state := Reg(new_hit_state)
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meta.io.state_req.bits.way_en := Reg(hit_way_oh)
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meta.io.state_req.bits.way_en := Reg(tag_match_way_oh)
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meta.io.state_req.valid := Reg(set_hit_state, resetVal = Bool(false))
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// pending store data, also used for AMO RHS
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@ -849,7 +847,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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p_store_idx := r_cpu_req_idx
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p_store_type := r_cpu_req_type
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p_store_cmd := r_cpu_req_cmd
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p_store_way_oh := Mux(r_replay_amo, r_way_oh, hit_way_oh)
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p_store_way_oh := Mux(r_replay_amo, r_way_oh, tag_match_way_oh)
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p_store_data := cpu_req_data
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}
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when (p_amo) {
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@ -858,8 +856,8 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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// miss handling
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mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
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mshr.io.req.bits.tag_miss := tag_miss || flusher.io.mshr_req.valid
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mshr.io.req.bits.old_state := meta_wb_mux.state
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mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
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mshr.io.req.bits.old_dirty := needsWriteback(meta_wb_mux.state) && !tag_match // don't wb upgrades
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mshr.io.req.bits.old_tag := meta_wb_mux.tag
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mshr.io.req.bits.tag := cpu_req_tag
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mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
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@ -867,7 +865,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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mshr.io.req.bits.offset := r_cpu_req_idx(offsetmsb,0)
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mshr.io.req.bits.cmd := r_cpu_req_cmd
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mshr.io.req.bits.typ := r_cpu_req_type
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mshr.io.req.bits.way_oh := replaced_way_oh
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mshr.io.req.bits.way_oh := Mux(tag_match, tag_match_way_oh, replaced_way_oh)
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mshr.io.req.bits.data := cpu_req_data
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mshr.io.mem_rep <> io.mem.xact_rep
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@ -932,9 +930,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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io.cpu.req_rdy := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
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io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
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io.cpu.resp_val := (tag_hit && !mshr.io.secondary_miss && !nack && r_req_read) || mshr.io.cpu_resp_val
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io.cpu.resp_val := (r_cpu_req_val && tag_hit && !mshr.io.secondary_miss && !nack && r_req_read) || mshr.io.cpu_resp_val
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io.cpu.resp_replay := mshr.io.cpu_resp_val
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io.cpu.resp_miss := r_cpu_req_val_ && (!tag_match || mshr.io.secondary_miss) && r_req_read
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io.cpu.resp_miss := r_cpu_req_val_ && (!tag_hit || mshr.io.secondary_miss) && r_req_read
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io.cpu.resp_tag := Mux(mshr.io.cpu_resp_val, mshr.io.cpu_resp_tag, r_cpu_req_tag)
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io.cpu.resp_type := loadgen.io.typ
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io.cpu.resp_data := loadgen.io.dout
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@ -24,12 +24,13 @@ class queue[T <: Data](entries: Int, pipe: Boolean = false, flushable: Boolean =
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{
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enq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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deq_ptr = Reg(resetVal = UFix(0, log2up(entries)))
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val pow2 = Bool((entries & (entries-1)) == 0)
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when (do_deq) {
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deq_ptr := deq_ptr + UFix(1)
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deq_ptr := Mux(!pow2 && deq_ptr === UFix(entries-1), UFix(0), deq_ptr + UFix(1))
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}
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when (do_enq) {
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enq_ptr := enq_ptr + UFix(1)
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enq_ptr := Mux(!pow2 && enq_ptr === UFix(entries-1), UFix(0), enq_ptr + UFix(1))
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}
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if (flushable) {
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when (io.flush) {
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