riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

move srcs into src dir, factoring out uncore consts into consts

Browse Source
This commit is contained in:
Huy Vo 2012-09-27 12:59:45 -07:00
parent aa7fd1f40b
commit fa8075570a
4 changed files with 31 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
uncore/coherence.scala → uncore/src/coherence.scala
View File

@ -1,4 +1,4 @@
package rocket
package uncore
import Chisel._
import Constants._

28
uncore/src/consts.scala Normal file
View File

@ -0,0 +1,28 @@
package uncore
import Chisel._
object Constants
{
val X_INIT_TYPE_MAX_BITS = 2
val X_REP_TYPE_MAX_BITS = 3
val P_REQ_TYPE_MAX_BITS = 2
val P_REP_TYPE_MAX_BITS = 3
val PADDR_BITS = 40;
val VADDR_BITS = 43;
val PGIDX_BITS = 13;
val PPN_BITS = PADDR_BITS-PGIDX_BITS;
val VPN_BITS = VADDR_BITS-PGIDX_BITS;
val ASID_BITS = 7;
val PERM_BITS = 6;
val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
val TILE_ID_BITS = log2Up(NTILES)+1
val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
val NGLOBAL_XACTS = 8
val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
}

2
uncore/llc.scala → uncore/src/llc.scala
View File

@ -1,4 +1,4 @@
package rocket
package uncore
import Chisel._
import Node._

2
uncore/uncore.scala → uncore/src/uncore.scala
View File

@ -1,4 +1,4 @@
package rocket
package uncore
import Chisel._
import Constants._