forgot to change package + using fromBits in memserdes instead of manual unpacking
This commit is contained in:
parent
9610622ab0
commit
08ab076217
@ -10,6 +10,9 @@ object Constants
|
||||
val HAVE_FPU = true
|
||||
val HAVE_VEC = true
|
||||
|
||||
val HTIF_WIDTH = 16
|
||||
val MEM_BACKUP_WIDTH = HTIF_WIDTH
|
||||
|
||||
val M_X = Bits("b????", 4);
|
||||
val M_XRD = Bits("b0000", 4); // int load
|
||||
val M_XWR = Bits("b0001", 4); // int store
|
||||
|
@ -1,4 +1,4 @@
|
||||
package rocket
|
||||
package uncore
|
||||
|
||||
import Chisel._
|
||||
import Node._
|
||||
@ -143,9 +143,7 @@ class MemDessert extends Component // test rig side
|
||||
|
||||
val req_cmd = in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (abits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
|
||||
io.wide.req_cmd.valid := state === s_cmd
|
||||
io.wide.req_cmd.bits.tag := req_cmd
|
||||
io.wide.req_cmd.bits.addr := req_cmd.toUFix >> UFix(io.wide.req_cmd.bits.tag.width + io.wide.req_cmd.bits.rw.width)
|
||||
io.wide.req_cmd.bits.rw := req_cmd(io.wide.req_cmd.bits.tag.width)
|
||||
io.wide.req_cmd.bits := io.wide.req_cmd.bits.fromBits(req_cmd)
|
||||
|
||||
io.wide.req_data.valid := state === s_data
|
||||
io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
|
||||
|
@ -1,4 +1,4 @@
|
||||
package rocket
|
||||
package uncore
|
||||
|
||||
import Chisel._
|
||||
import Constants._
|
||||
|
Loading…
Reference in New Issue
Block a user