Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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commit
6e32cc8b20
@ -147,8 +147,8 @@ trait FourStateCoherence extends CoherencePolicy {
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def isHit ( cmd: Bits, state: UFix): Bool = {
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val (read, write) = cpuCmdToRW(cmd)
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((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
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(write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
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Mux(write, (state === tileExclusiveClean || state === tileExclusiveDirty),
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(state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty))
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}
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//TODO: do we need isPresent() for determining that a line needs to be
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@ -600,7 +600,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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conflicts(i) := t.busy && x_init.valid && coherenceConflict(t.addr, x_init.bits.address)
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}
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x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
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want_to_abort_arr(j) := conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits))
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want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && transactionInitHasData(x_init.bits)))
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x_abort.valid := Bool(false)
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switch(abort_state_arr(j)) {
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