1
0
Commit Graph

89 Commits

Author SHA1 Message Date
d896ccbd43 Merge branch 'master' into chisel-v2
Conflicts:
	src/main/scala/htif.scala
2013-09-05 16:11:53 -07:00
44e92edf92 fix scr parameterization bug 2013-08-24 22:42:51 -07:00
3895b75a56 Support non-power-of-2 BTBs; prefer invalid entries 2013-08-24 17:33:11 -07:00
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
ae02ebd153 Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala
2013-08-15 16:35:27 -07:00
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
387cf0ebe0 reset -> resetVal, getReset -> reset 2013-08-12 20:51:54 -07:00
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
de313d97de Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2013-08-02 16:30:09 -07:00
4eaab214d2 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:29:51 -07:00
3132db4f90 Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity. 2013-07-30 16:36:28 -07:00
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
db5a060c7d fix io dir 2013-04-10 13:47:30 -07:00
8b439ef20d only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
2013-04-04 17:07:08 -07:00
d43f484feb take interrupts on nonzero fromhost values 2013-04-04 17:07:08 -07:00
d4a3351cfc expose pending interrupts in status register 2013-04-04 17:07:08 -07:00
95f0a688e9 Merge branch 'release-xacts'
Conflicts:
	src/htif.scala
	src/icache.scala
	src/nbdcache.scala
	src/tile.scala
2013-03-20 17:37:50 -07:00
6d2541aced nTiles -> nClients in LogicalNetworkConfig 2013-03-20 14:12:36 -07:00
5b9f938263 correctly sign-extend badvaddr, epc, and ebase 2013-01-24 17:54:59 -08:00
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
e9752f1d72 pipeline host pcr access 2012-12-06 14:22:07 -08:00
4608660f6e torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
9c857b83f0 refactor PCR file 2012-11-27 01:28:06 -08:00
29bc361d6c remove global constants; disentangle hwacha a bit 2012-11-17 17:24:08 -08:00
5a7777fe4d clock gate integer datapath more aggressively 2012-11-17 06:48:44 -08:00
7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
5773cbb68a rejigger htif to use UncoreConfiguration 2012-10-18 17:26:03 -07:00
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
b94e6915ab refactor IPIs; use new tohost/fromhost protocol 2012-08-03 19:00:34 -07:00
130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
a2f6d01c1b add programmable coreid register 2012-05-09 03:09:22 -07:00
e0e1cd5d32 add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
2012-05-08 22:58:00 -07:00
86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
8c50c81b81 drop vec_irq_aux pcr register, now everything goes through badvaddr 2012-03-17 14:03:57 -07:00
b19d783fbd add vector irq handler 2012-03-14 14:15:28 -07:00
040d62f372 refactored vector exception handling interface 2012-03-13 23:45:34 -07:00
b100544b25 datapath to read out vector state 2012-03-13 23:45:34 -07:00