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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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de313d97de
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2013-08-02 16:30:09 -07:00 |
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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db5a060c7d
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fix io dir
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2013-04-10 13:47:30 -07:00 |
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8b439ef20d
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only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
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d43f484feb
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take interrupts on nonzero fromhost values
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2013-04-04 17:07:08 -07:00 |
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d4a3351cfc
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expose pending interrupts in status register
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2013-04-04 17:07:08 -07:00 |
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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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6d2541aced
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
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5b9f938263
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correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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5773cbb68a
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rejigger htif to use UncoreConfiguration
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2012-10-18 17:26:03 -07:00 |
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
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b94e6915ab
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refactor IPIs; use new tohost/fromhost protocol
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2012-08-03 19:00:34 -07:00 |
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130fa95ed6
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expand HTIF's PCR register space
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2012-07-27 14:52:39 -07:00 |
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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a2f6d01c1b
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add programmable coreid register
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2012-05-09 03:09:22 -07:00 |
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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3a487ac89b
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improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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8c50c81b81
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drop vec_irq_aux pcr register, now everything goes through badvaddr
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2012-03-17 14:03:57 -07:00 |
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b19d783fbd
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add vector irq handler
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2012-03-14 14:15:28 -07:00 |
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040d62f372
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refactored vector exception handling interface
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2012-03-13 23:45:34 -07:00 |
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b100544b25
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datapath to read out vector state
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2012-03-13 23:45:34 -07:00 |
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